Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.


software_version_and_target_device
betaFALSE build_version2405991
date_generatedFri Sep 27 21:37:44 2019 os_platformLIN64
product_versionVivado v2018.3 (64-bit) project_idd5e5270f3fad41bc9a6292fe7c5e6efc
project_iteration1 random_idadc0d93900c15994bdc1443c46659ce8
registration_idadc0d93900c15994bdc1443c46659ce8 route_designTRUE
target_devicexc7a35ti target_familyartix7
target_packagecsg324 target_speed-1L
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-3520M CPU @ 2.90GHz cpu_speed3400.023 MHz
os_nameDebian os_releaseDebian GNU/Linux 9.8 (stretch)
system_ram6.000 GB total_processors1

vivado_usage
gui_handlers
addrepositoryinfodialog_ok=1 addsrcwizard_specify_hdl_netlist_block_design=2 addsrcwizard_specify_or_create_constraint_files=2 addsrcwizard_specify_simulation_specific_hdl_files=2
basedialog_ok=3 boardchooser_board_table=2 constraintschooserpanel_add_files=1 coreandinterfacesbasetreetablepanel_add_repository=1
coretreetablepanel_core_tree_table=7 filesetpanel_file_set_panel_tree=17 flownavigatortreepanel_flow_navigator_tree=5 gettingstartedview_create_new_project=1
graphicalview_zoom_out=27 pacommandnames_add_sources=3 pacommandnames_auto_update_hier=4 pacommandnames_run_bitgen=1
pacommandnames_simulation_live_break=9 pacommandnames_simulation_live_restart=1 pacommandnames_simulation_live_run_all=9 pacommandnames_simulation_relaunch=10
pacommandnames_simulation_run_behavioral=1 pacommandnames_toggle_view_nav=1 paviews_project_summary=1 planaheadtab_show_flow_navigator=1
progressdialog_background=6 projectnamechooser_choose_project_location=5 projectnamechooser_project_name=1 rdicommands_save_file=11
rdiviews_waveform_viewer=29 simpleoutputproductdialog_generate_output_products_immediately=1 simpleoutputproductdialog_synthesize_design_globally=1 simulationobjectspanel_simulation_objects_tree_table=2
simulationscopespanel_simulate_scope_table=5 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=2 srcmenu_ip_hierarchy=5 tclconsoleview_clear_all_output_in_tcl_console=3
waveformnametree_waveform_name_tree=10 waveformview_goto_time_0=1 waveformview_next_transition=32 waveformview_previous_transition=22
java_command_handlers
addsources=3 coreview=3 customizecore=1 newproject=1
runbitgen=1 runimplementation=1 simulationbreak=9 simulationrelaunch=7
simulationrestart=1 simulationrun=1 simulationrunall=9 toggleviewnavigator=1
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=1 export_simulation_ies=1
export_simulation_modelsim=1 export_simulation_questa=1 export_simulation_riviera=1 export_simulation_vcs=1
export_simulation_xsim=1 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=15 simulator_language=Mixed srcsetcount=4 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=1 fdce=44 fdpe=11 fdre=63
gnd=6 ibuf=7 lut1=3 lut2=9
lut3=26 lut4=35 lut5=32 lut6=26
obuf=5 rams32=16 vcc=4
pre_unisim_transformation
bufg=1 fdce=44 fdpe=11 fdre=63
gnd=6 ibuf=7 lut1=3 lut2=9
lut3=26 lut4=35 lut5=32 lut6=26
obuf=5 ram32x1s=16 vcc=4

ip_statistics
hls_core/1
core_container=NA iptotal=1 x_ipcorerevision=1909271933 x_iplanguage=VERILOG
x_iplibrary=hls x_ipname=hls_core x_ipproduct=Vivado 2018.3 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
hls_ip_2018_3/1
core_container=NA hls_input_arch=others hls_input_clock=10.000000 hls_input_fixed=0
hls_input_float=0 hls_input_part=xc7a35ticsg324-1l hls_input_type=c hls_syn_clock=4.901750
hls_syn_dsp=0 hls_syn_ff=44 hls_syn_lat=1 hls_syn_lut=213
hls_syn_mem=0 hls_syn_tpt=none hls_version=2018_3 iptotal=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=1 fdce_functional_category=Flop & Latch fdce_used=44
fdpe_functional_category=Flop & Latch fdpe_used=11 fdre_functional_category=Flop & Latch fdre_used=57
ibuf_functional_category=IO ibuf_used=7 lut1_functional_category=LUT lut1_used=3
lut2_functional_category=LUT lut2_used=9 lut3_functional_category=LUT lut3_used=28
lut4_functional_category=LUT lut4_used=35 lut5_functional_category=LUT lut5_used=32
lut6_functional_category=LUT lut6_used=24 obuf_functional_category=IO obuf_used=5
rams32_functional_category=Distributed Memory rams32_used=16
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=16 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=100 lut_as_logic_util_percentage=0.48 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=16 lut_as_memory_util_percentage=0.17 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=112 register_as_flip_flop_util_percentage=0.27
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=116 slice_luts_util_percentage=0.56
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=112 slice_registers_util_percentage=0.27
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=16 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=100 lut_as_logic_util_percentage=0.48 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=16 lut_as_memory_util_percentage=0.17 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=29 lut_in_front_of_the_register_is_used_fixed=29 lut_in_front_of_the_register_is_used_used=7
register_driven_from_outside_the_slice_fixed=7 register_driven_from_outside_the_slice_used=36 register_driven_from_within_the_slice_fixed=36 register_driven_from_within_the_slice_used=76
slice_available=8150 slice_fixed=0 slice_registers_available=41600 slice_registers_fixed=0
slice_registers_used=112 slice_registers_util_percentage=0.27 slice_used=40 slice_util_percentage=0.49
slicel_fixed=0 slicel_used=28 slicem_fixed=0 slicem_used=12
unique_control_sets_available=8150 unique_control_sets_fixed=8150 unique_control_sets_used=15 unique_control_sets_util_percentage=0.18
using_o5_and_o6_fixed=0.18 using_o5_and_o6_used=0 using_o5_output_only_fixed=0 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=16
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35ticsg324-1L
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=topmodule -verilog_define=default::[not_specified]
usage
elapsed=00:00:16s hls_ip=1 memory_gain=428.148MB memory_peak=1915.758MB

xsim
command_line_options
-sim_mode=behavioral -sim_type=default::