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          </xilinx:configElementInfos>
          <xilinx:boundaryDescriptionInfo>
            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{
              &quot;schema&quot;: &quot;xilinx.com:schema:json_boundary:1.0&quot;,
              &quot;boundary&quot;: {
                &quot;ports&quot;: {
                  &quot;s_axi_aclk&quot;: [ { &quot;direction&quot;: &quot;in&quot; } ],
                  &quot;s_axi_aresetn&quot;: [ { &quot;direction&quot;: &quot;in&quot; } ],
                  &quot;s_axi_awaddr&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;size_left&quot;: &quot;8&quot;, &quot;size_right&quot;: &quot;0&quot; } ],
                  &quot;s_axi_awvalid&quot;: [ { &quot;direction&quot;: &quot;in&quot; } ],
                  &quot;s_axi_awready&quot;: [ { &quot;direction&quot;: &quot;out&quot; } ],
                  &quot;s_axi_wdata&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;size_left&quot;: &quot;31&quot;, &quot;size_right&quot;: &quot;0&quot; } ],
                  &quot;s_axi_wstrb&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;size_left&quot;: &quot;3&quot;, &quot;size_right&quot;: &quot;0&quot; } ],
                  &quot;s_axi_wvalid&quot;: [ { &quot;direction&quot;: &quot;in&quot; } ],
                  &quot;s_axi_wready&quot;: [ { &quot;direction&quot;: &quot;out&quot; } ],
                  &quot;s_axi_bresp&quot;: [ { &quot;direction&quot;: &quot;out&quot;, &quot;size_left&quot;: &quot;1&quot;, &quot;size_right&quot;: &quot;0&quot; } ],
                  &quot;s_axi_bvalid&quot;: [ { &quot;direction&quot;: &quot;out&quot; } ],
                  &quot;s_axi_bready&quot;: [ { &quot;direction&quot;: &quot;in&quot; } ],
                  &quot;s_axi_araddr&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;size_left&quot;: &quot;8&quot;, &quot;size_right&quot;: &quot;0&quot; } ],
                  &quot;s_axi_arvalid&quot;: [ { &quot;direction&quot;: &quot;in&quot; } ],
                  &quot;s_axi_arready&quot;: [ { &quot;direction&quot;: &quot;out&quot; } ],
                  &quot;s_axi_rdata&quot;: [ { &quot;direction&quot;: &quot;out&quot;, &quot;size_left&quot;: &quot;31&quot;, &quot;size_right&quot;: &quot;0&quot; } ],
                  &quot;s_axi_rresp&quot;: [ { &quot;direction&quot;: &quot;out&quot;, &quot;size_left&quot;: &quot;1&quot;, &quot;size_right&quot;: &quot;0&quot; } ],
                  &quot;s_axi_rvalid&quot;: [ { &quot;direction&quot;: &quot;out&quot; } ],
                  &quot;s_axi_rready&quot;: [ { &quot;direction&quot;: &quot;in&quot; } ],
                  &quot;intr&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;size_left&quot;: &quot;1&quot;, &quot;size_right&quot;: &quot;0&quot; } ],
                  &quot;processor_clk&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;driver_value&quot;: &quot;0&quot; } ],
                  &quot;processor_rst&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;driver_value&quot;: &quot;0&quot; } ],
                  &quot;irq&quot;: [ { &quot;direction&quot;: &quot;out&quot; } ],
                  &quot;processor_ack&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;size_left&quot;: &quot;1&quot;, &quot;size_right&quot;: &quot;0&quot;, &quot;driver_value&quot;: &quot;0&quot; } ],
                  &quot;interrupt_address&quot;: [ { &quot;direction&quot;: &quot;out&quot;, &quot;size_left&quot;: &quot;31&quot;, &quot;size_right&quot;: &quot;0&quot; } ]
                },
                &quot;interfaces&quot;: {
                  &quot;s_axi&quot;: {
                    &quot;vlnv&quot;: &quot;xilinx.com:interface:aximm:1.0&quot;,
                    &quot;abstraction_type&quot;: &quot;xilinx.com:interface:aximm_rtl:1.0&quot;,
                    &quot;mode&quot;: &quot;slave&quot;,
                    &quot;memory_map_ref&quot;: &quot;S_AXI&quot;,
                    &quot;parameters&quot;: {
                      &quot;DATA_WIDTH&quot;: [ { &quot;value&quot;: &quot;32&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;PROTOCOL&quot;: [ { &quot;value&quot;: &quot;AXI4LITE&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;FREQ_HZ&quot;: [ { &quot;value&quot;: &quot;100000000&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;ID_WIDTH&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;ADDR_WIDTH&quot;: [ { &quot;value&quot;: &quot;9&quot;, &quot;value_src&quot;: &quot;auto&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;AWUSER_WIDTH&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;ARUSER_WIDTH&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;WUSER_WIDTH&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;RUSER_WIDTH&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;BUSER_WIDTH&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;READ_WRITE_MODE&quot;: [ { &quot;value&quot;: &quot;READ_WRITE&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;HAS_BURST&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;HAS_LOCK&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;HAS_PROT&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;HAS_CACHE&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;HAS_QOS&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;HAS_REGION&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;HAS_WSTRB&quot;: [ { &quot;value&quot;: &quot;1&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;HAS_BRESP&quot;: [ { &quot;value&quot;: &quot;1&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;HAS_RRESP&quot;: [ { &quot;value&quot;: &quot;1&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;SUPPORTS_NARROW_BURST&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;NUM_READ_OUTSTANDING&quot;: [ { &quot;value&quot;: &quot;2&quot;, &quot;value_src&quot;: &quot;default_prop&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;NUM_WRITE_OUTSTANDING&quot;: [ { &quot;value&quot;: &quot;2&quot;, &quot;value_src&quot;: &quot;default_prop&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;MAX_BURST_LENGTH&quot;: [ { &quot;value&quot;: &quot;1&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;PHASE&quot;: [ { &quot;value&quot;: &quot;0.0&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;float&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;CLK_DOMAIN&quot;: [ { &quot;value&quot;: &quot;/clk_wiz_0_clk_out1&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;NUM_READ_THREADS&quot;: [ { &quot;value&quot;: &quot;1&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;NUM_WRITE_THREADS&quot;: [ { &quot;value&quot;: &quot;1&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;RUSER_BITS_PER_BYTE&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;WUSER_BITS_PER_BYTE&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;INSERT_VIP&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;resolve_type&quot;: &quot;user&quot;, &quot;format&quot;: &quot;long&quot;, &quot;usage&quot;: &quot;simulation.rtl&quot;, &quot;is_static_object&quot;: false } ]
                    },
                    &quot;port_maps&quot;: {
                      &quot;ARADDR&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_araddr&quot; } ],
                      &quot;ARREADY&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_arready&quot; } ],
                      &quot;ARVALID&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_arvalid&quot; } ],
                      &quot;AWADDR&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_awaddr&quot; } ],
                      &quot;AWREADY&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_awready&quot; } ],
                      &quot;AWVALID&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_awvalid&quot; } ],
                      &quot;BREADY&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_bready&quot; } ],
                      &quot;BRESP&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_bresp&quot; } ],
                      &quot;BVALID&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_bvalid&quot; } ],
                      &quot;RDATA&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_rdata&quot; } ],
                      &quot;RREADY&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_rready&quot; } ],
                      &quot;RRESP&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_rresp&quot; } ],
                      &quot;RVALID&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_rvalid&quot; } ],
                      &quot;WDATA&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_wdata&quot; } ],
                      &quot;WREADY&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_wready&quot; } ],
                      &quot;WSTRB&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_wstrb&quot; } ],
                      &quot;WVALID&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_wvalid&quot; } ]
                    }
                  },
                  &quot;s_axi_aclk&quot;: {
                    &quot;vlnv&quot;: &quot;xilinx.com:signal:clock:1.0&quot;,
                    &quot;abstraction_type&quot;: &quot;xilinx.com:signal:clock_rtl:1.0&quot;,
                    &quot;mode&quot;: &quot;slave&quot;,
                    &quot;parameters&quot;: {
                      &quot;ASSOCIATED_BUSIF&quot;: [ { &quot;value&quot;: &quot;s_axi&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;ASSOCIATED_RESET&quot;: [ { &quot;value&quot;: &quot;s_axi_aresetn&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;FREQ_HZ&quot;: [ { &quot;value&quot;: &quot;100000000&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;FREQ_TOLERANCE_HZ&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;PHASE&quot;: [ { &quot;value&quot;: &quot;0.0&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;float&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;CLK_DOMAIN&quot;: [ { &quot;value&quot;: &quot;/clk_wiz_0_clk_out1&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;ASSOCIATED_PORT&quot;: [ { &quot;value&quot;: &quot;&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;INSERT_VIP&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;resolve_type&quot;: &quot;user&quot;, &quot;format&quot;: &quot;long&quot;, &quot;usage&quot;: &quot;simulation.rtl&quot;, &quot;is_static_object&quot;: false } ]
                    },
                    &quot;port_maps&quot;: {
                      &quot;CLK&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_aclk&quot; } ]
                    }
                  },
                  &quot;s_resetn&quot;: {
                    &quot;vlnv&quot;: &quot;xilinx.com:signal:reset:1.0&quot;,
                    &quot;abstraction_type&quot;: &quot;xilinx.com:signal:reset_rtl:1.0&quot;,
                    &quot;mode&quot;: &quot;slave&quot;,
                    &quot;parameters&quot;: {
                      &quot;POLARITY&quot;: [ { &quot;value&quot;: &quot;ACTIVE_LOW&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;INSERT_VIP&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;resolve_type&quot;: &quot;user&quot;, &quot;format&quot;: &quot;long&quot;, &quot;usage&quot;: &quot;simulation.rtl&quot;, &quot;is_static_object&quot;: false } ]
                    },
                    &quot;port_maps&quot;: {
                      &quot;RST&quot;: [ { &quot;physical_name&quot;: &quot;s_axi_aresetn&quot; } ]
                    }
                  },
                  &quot;proc_clock&quot;: {
                    &quot;vlnv&quot;: &quot;xilinx.com:signal:clock:1.0&quot;,
                    &quot;abstraction_type&quot;: &quot;xilinx.com:signal:clock_rtl:1.0&quot;,
                    &quot;mode&quot;: &quot;slave&quot;,
                    &quot;parameters&quot;: {
                      &quot;ASSOCIATED_BUSIF&quot;: [ { &quot;value&quot;: &quot;interrupt&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;ASSOCIATED_RESET&quot;: [ { &quot;value&quot;: &quot;processor_rst&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;FREQ_HZ&quot;: [ { &quot;value&quot;: &quot;100000000&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;FREQ_TOLERANCE_HZ&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;PHASE&quot;: [ { &quot;value&quot;: &quot;0.0&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;float&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;CLK_DOMAIN&quot;: [ { &quot;value&quot;: &quot;/clk_wiz_0_clk_out1&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;ASSOCIATED_PORT&quot;: [ { &quot;value&quot;: &quot;&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;INSERT_VIP&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;resolve_type&quot;: &quot;user&quot;, &quot;format&quot;: &quot;long&quot;, &quot;usage&quot;: &quot;simulation.rtl&quot;, &quot;is_static_object&quot;: false } ]
                    },
                    &quot;port_maps&quot;: {
                      &quot;CLK&quot;: [ { &quot;physical_name&quot;: &quot;processor_clk&quot; } ]
                    }
                  },
                  &quot;proc_reset&quot;: {
                    &quot;vlnv&quot;: &quot;xilinx.com:signal:reset:1.0&quot;,
                    &quot;abstraction_type&quot;: &quot;xilinx.com:signal:reset_rtl:1.0&quot;,
                    &quot;mode&quot;: &quot;slave&quot;,
                    &quot;parameters&quot;: {
                      &quot;POLARITY&quot;: [ { &quot;value&quot;: &quot;ACTIVE_HIGH&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;TYPE&quot;: [ { &quot;value&quot;: &quot;PROCESSOR&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;INSERT_VIP&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;resolve_type&quot;: &quot;user&quot;, &quot;format&quot;: &quot;long&quot;, &quot;usage&quot;: &quot;simulation.rtl&quot;, &quot;is_static_object&quot;: false } ]
                    },
                    &quot;port_maps&quot;: {
                      &quot;RST&quot;: [ { &quot;physical_name&quot;: &quot;processor_rst&quot; } ]
                    }
                  },
                  &quot;interrupt&quot;: {
                    &quot;vlnv&quot;: &quot;xilinx.com:interface:mbinterrupt:1.0&quot;,
                    &quot;abstraction_type&quot;: &quot;xilinx.com:interface:mbinterrupt_rtl:1.0&quot;,
                    &quot;mode&quot;: &quot;master&quot;,
                    &quot;parameters&quot;: {
                      &quot;SENSITIVITY&quot;: [ { &quot;value&quot;: &quot;LEVEL_HIGH&quot;, &quot;value_src&quot;: &quot;user&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;LOW_LATENCY&quot;: [ { &quot;value&quot;: &quot;1&quot;, &quot;value_src&quot;: &quot;user&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ]
                    },
                    &quot;port_maps&quot;: {
                      &quot;ACK&quot;: [ { &quot;physical_name&quot;: &quot;processor_ack&quot; } ],
                      &quot;ADDRESS&quot;: [ { &quot;physical_name&quot;: &quot;interrupt_address&quot; } ],
                      &quot;INTERRUPT&quot;: [ { &quot;physical_name&quot;: &quot;irq&quot; } ]
                    }
                  },
                  &quot;interrupt_input&quot;: {
                    &quot;vlnv&quot;: &quot;xilinx.com:signal:interrupt:1.0&quot;,
                    &quot;abstraction_type&quot;: &quot;xilinx.com:signal:interrupt_rtl:1.0&quot;,
                    &quot;mode&quot;: &quot;slave&quot;,
                    &quot;parameters&quot;: {
                      &quot;SENSITIVITY&quot;: [ { &quot;value&quot;: &quot;EDGE_RISING:LEVEL_HIGH&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;PortWidth&quot;: [ { &quot;value&quot;: &quot;2&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ]
                    },
                    &quot;port_maps&quot;: {
                      &quot;INTERRUPT&quot;: [ { &quot;physical_name&quot;: &quot;intr&quot; } ]
                    }
                  }
                },
                &quot;memory_maps&quot;: {
                  &quot;S_AXI&quot;: {
                    &quot;display_name&quot;: &quot;S_AXI_MEM&quot;,
                    &quot;description&quot;: &quot;Memory Map for S_AXI&quot;,
                    &quot;address_blocks&quot;: {
                      &quot;Reg&quot;: {
                        &quot;base_address&quot;: &quot;0&quot;,
                        &quot;range&quot;: &quot;4096&quot;,
                        &quot;display_name&quot;: &quot;Reg&quot;,
                        &quot;description&quot;: &quot;Register Block&quot;,
                        &quot;usage&quot;: &quot;register&quot;,
                        &quot;access&quot;: &quot;read-write&quot;,
                        &quot;registers&quot;: {
                          &quot;ISR&quot;: {
                            &quot;address_offset&quot;: &quot;0x0&quot;,
                            &quot;size&quot;: 2,
                            &quot;display_name&quot;: &quot;Interrupt Status Register&quot;,
                            &quot;description&quot;: &quot;Interrupt Status Register&quot;,
                            &quot;is_volatile&quot;: true,
                            &quot;access&quot;: &quot;read-write&quot;,
                            &quot;reset_value&quot;: &quot;0x0&quot;,
                            &quot;fields&quot;: {
                              &quot;INT&quot;: {
                                &quot;bit_offset&quot;: 0,
                                &quot;bit_width&quot;: 2,
                                &quot;display_name&quot;: &quot;Active Interrupt Signal&quot;,
                                &quot;description&quot;: &quot;Interrupt Status Register.\nFor each bit up to number of periperhal interrupts:\n  R - Reads active interrupt signal.\n  W - No effect after MER HIE bit has been set, otherwise writes active interrupt signal.\nFor remaining bits defined by number of software interrupts:\n  R - Reads software interrupt value.\n  W - Writes software interrupt value.\n&quot;,
                                &quot;is_volatile&quot;: true,
                                &quot;access&quot;: &quot;read-write&quot;
                              }
                            }
                          },
                          &quot;IPR&quot;: {
                            &quot;address_offset&quot;: &quot;0x4&quot;,
                            &quot;size&quot;: 2,
                            &quot;display_name&quot;: &quot;Interrupt Pending Register&quot;,
                            &quot;description&quot;: &quot;Interrupt Pending Register&quot;,
                            &quot;is_volatile&quot;: true,
                            &quot;access&quot;: &quot;read-only&quot;,
                            &quot;reset_value&quot;: &quot;0x0&quot;,
                            &quot;fields&quot;: {
                              &quot;INT&quot;: {
                                &quot;bit_offset&quot;: 0,
                                &quot;bit_width&quot;: 2,
                                &quot;display_name&quot;: &quot;Pending Interrupt Signal&quot;,
                                &quot;description&quot;: &quot;Interrupt Pending Register.\nFor each bit:\n  R - Reads logical AND of bits in ISR and IER.\n  W - No effect.\n&quot;,
                                &quot;is_volatile&quot;: true,
                                &quot;access&quot;: &quot;read-only&quot;
                              }
                            }
                          },
                          &quot;IER&quot;: {
                            &quot;address_offset&quot;: &quot;0x8&quot;,
                            &quot;size&quot;: 2,
                            &quot;display_name&quot;: &quot;Interrupt Enable Register&quot;,
                            &quot;description&quot;: &quot;Interrupt Enable Register&quot;,
                            &quot;is_volatile&quot;: true,
                            &quot;access&quot;: &quot;read-write&quot;,
                            &quot;reset_value&quot;: &quot;0x0&quot;,
                            &quot;fields&quot;: {
                              &quot;INT&quot;: {
                                &quot;bit_offset&quot;: 0,
                                &quot;bit_width&quot;: 2,
                                &quot;display_name&quot;: &quot;Interrupt Enable&quot;,
                                &quot;description&quot;: &quot;Interrupt Enable Register.\nFor each bit:\n  R - Reads interrupt enable value.\n  W - Writes interrupt enable value.\n&quot;,
                                &quot;is_volatile&quot;: true,
                                &quot;access&quot;: &quot;read-write&quot;
                              }
                            }
                          },
                          &quot;IAR&quot;: {
                            &quot;address_offset&quot;: &quot;0xC&quot;,
                            &quot;size&quot;: 2,
                            &quot;display_name&quot;: &quot;Interrupt Acknowledge Register&quot;,
                            &quot;description&quot;: &quot;Interrupt Acknowledge Register&quot;,
                            &quot;is_volatile&quot;: true,
                            &quot;access&quot;: &quot;write-only&quot;,
                            &quot;reset_value&quot;: &quot;0x0&quot;,
                            &quot;fields&quot;: {
                              &quot;INT&quot;: {
                                &quot;bit_offset&quot;: 0,
                                &quot;bit_width&quot;: 2,
                                &quot;display_name&quot;: &quot;Interrupt Acknowledge&quot;,
                                &quot;description&quot;: &quot;Interrupt Acknowledge Register.\nFor each bit:\n  W - Acknowledge interrupt.\n&quot;,
                                &quot;is_volatile&quot;: true,
                                &quot;access&quot;: &quot;write-only&quot;
                              }
                            }
                          },
                          &quot;SIE&quot;: {
                            &quot;address_offset&quot;: &quot;0x10&quot;,
                            &quot;size&quot;: 2,
                            &quot;display_name&quot;: &quot;Set Interrupt Enables&quot;,
                            &quot;description&quot;: &quot;Set Interrupt Enables&quot;,
                            &quot;is_volatile&quot;: true,
                            &quot;access&quot;: &quot;read-write&quot;,
                            &quot;reset_value&quot;: &quot;0x0&quot;,
                            &quot;fields&quot;: {
                              &quot;INT&quot;: {
                                &quot;bit_offset&quot;: 0,
                                &quot;bit_width&quot;: 2,
                                &quot;display_name&quot;: &quot;Set Interrupt Enable&quot;,
                                &quot;description&quot;: &quot;Set Interrupt Enables\nFor each bit:\n  R - Reads active interrupt.\n  W - Writing 1 enables the interrupt, writing 0 has no effect.\n&quot;,
                                &quot;is_volatile&quot;: true,
                                &quot;access&quot;: &quot;read-write&quot;
                              }
                            }
                          },
                          &quot;CIE&quot;: {
                            &quot;address_offset&quot;: &quot;0x14&quot;,
                            &quot;size&quot;: 2,
                            &quot;display_name&quot;: &quot;Clear Interrupt Enables&quot;,
                            &quot;description&quot;: &quot;Clear Interrupt Enables&quot;,
                            &quot;is_volatile&quot;: true,
                            &quot;access&quot;: &quot;read-write&quot;,
                            &quot;reset_value&quot;: &quot;0x0&quot;,
                            &quot;fields&quot;: {
                              &quot;INT&quot;: {
                                &quot;bit_offset&quot;: 0,
                                &quot;bit_width&quot;: 2,
                                &quot;display_name&quot;: &quot;Clear Interrupt Enable&quot;,
                                &quot;description&quot;: &quot;Clear Interrupt Enables\nFor each bit:\n  R - Reads active interrupt.\n  W - Writing 1 disables the interrupt, writing 0 has no effect.\n&quot;,
                                &quot;is_volatile&quot;: true,
                                &quot;access&quot;: &quot;read-write&quot;
                              }
                            }
                          },
                          &quot;IVR&quot;: {
                            &quot;address_offset&quot;: &quot;0x18&quot;,
                            &quot;size&quot;: 5,
                            &quot;display_name&quot;: &quot;Interrupt Vector Register&quot;,
                            &quot;description&quot;: &quot;Interrupt Vector Register&quot;,
                            &quot;is_volatile&quot;: true,
                            &quot;access&quot;: &quot;read-only&quot;,
                            &quot;reset_value&quot;: &quot;0x0&quot;,
                            &quot;fields&quot;: {
                              &quot;IVN&quot;: {
                                &quot;bit_offset&quot;: 0,
                                &quot;bit_width&quot;: 5,
                                &quot;display_name&quot;: &quot;Interrupt Vector Number&quot;,
                                &quot;description&quot;: &quot;Interrupt Vector Number.\n  R - Reads ordinal of highest priority, enabled, active interrupt.\n&quot;,
                                &quot;is_volatile&quot;: true,
                                &quot;access&quot;: &quot;read-only&quot;
                              }
                            }
                          },
                          &quot;MER&quot;: {
                            &quot;address_offset&quot;: &quot;0x1C&quot;,
                            &quot;size&quot;: 2,
                            &quot;display_name&quot;: &quot;Master Enable Register&quot;,
                            &quot;description&quot;: &quot;Master Enable Register&quot;,
                            &quot;is_volatile&quot;: true,
                            &quot;access&quot;: &quot;read-write&quot;,
                            &quot;reset_value&quot;: &quot;0x0&quot;,
                            &quot;fields&quot;: {
                              &quot;ME&quot;: {
                                &quot;bit_offset&quot;: 0,
                                &quot;bit_width&quot;: 1,
                                &quot;display_name&quot;: &quot;Master IRQ Enable&quot;,
                                &quot;description&quot;: &quot;Master IRQ Enable.\n  0 - All interrupts disabled.\n  1 - All interrupts can be enabled.\n&quot;,
                                &quot;is_volatile&quot;: true,
                                &quot;access&quot;: &quot;read-write&quot;
                              },
                              &quot;HIE&quot;: {
                                &quot;bit_offset&quot;: 1,
                                &quot;bit_width&quot;: 1,
                                &quot;display_name&quot;: &quot;Hardware Interrupt Enable&quot;,
                                &quot;description&quot;: &quot;Hardware Interrupt Enable.\n  0 - HW interrupts disabled.\n  1 - HW interrupts enabled.\n&quot;,
                                &quot;is_volatile&quot;: true,
                                &quot;access&quot;: &quot;read-write&quot;
                              }
                            }
                          },
                          &quot;IMR&quot;: {
                            &quot;address_offset&quot;: &quot;0x20&quot;,
                            &quot;size&quot;: 2,
                            &quot;display_name&quot;: &quot;Interrupt Mode Register&quot;,
                            &quot;description&quot;: &quot;Interrupt Mode Register&quot;,
                            &quot;is_volatile&quot;: true,
                            &quot;access&quot;: &quot;read-write&quot;,
                            &quot;reset_value&quot;: &quot;0x0&quot;,
                            &quot;fields&quot;: {
                              &quot;INT&quot;: {
                                &quot;bit_offset&quot;: 0,
                                &quot;bit_width&quot;: 2,
                                &quot;display_name&quot;: &quot;Interrupt Mode&quot;,
                                &quot;description&quot;: &quot;Interrupt Mode Register.\nFor each bit:\n  R - Reads interrupt mode.\n  W - Sets interrupt mode, where 0 is normal mode and 1 is fast mode.\n&quot;,
                                &quot;is_volatile&quot;: true,
                                &quot;access&quot;: &quot;read-write&quot;
                              }
                            }
                          },
                          &quot;IVAR[0]&quot;: {
                            &quot;address_offset&quot;: &quot;0x100&quot;,
                            &quot;size&quot;: 32,
                            &quot;display_name&quot;: &quot;Interrupt Vector Address Register 0&quot;,
                            &quot;description&quot;: &quot;Interrupt Vector Address Register 0&quot;,
                            &quot;is_volatile&quot;: true,
                            &quot;access&quot;: &quot;read-write&quot;,
                            &quot;reset_value&quot;: &quot;0x000000010&quot;,
                            &quot;fields&quot;: {
                              &quot;IVA&quot;: {
                                &quot;bit_offset&quot;: 0,
                                &quot;bit_width&quot;: 32,
                                &quot;display_name&quot;: &quot;Interrupt Vector Address&quot;,
                                &quot;description&quot;: &quot;Interrupt vector address of active interrupt 0 with highest priority.\n&quot;,
                                &quot;is_volatile&quot;: true,
                                &quot;access&quot;: &quot;read-write&quot;
                              }
                            }
                          },
                          &quot;IVAR[1]&quot;: {
                            &quot;address_offset&quot;: &quot;0x104&quot;,
                            &quot;size&quot;: 32,
                            &quot;display_name&quot;: &quot;Interrupt Vector Address Register 1&quot;,
                            &quot;description&quot;: &quot;Interrupt Vector Address Register 1&quot;,
                            &quot;is_volatile&quot;: true,
                            &quot;access&quot;: &quot;read-write&quot;,
                            &quot;reset_value&quot;: &quot;0x000000010&quot;,
                            &quot;fields&quot;: {
                              &quot;IVA&quot;: {
                                &quot;bit_offset&quot;: 0,
                                &quot;bit_width&quot;: 32,
                                &quot;display_name&quot;: &quot;Interrupt Vector Address&quot;,
                                &quot;description&quot;: &quot;Interrupt vector address of active interrupt 1 with highest priority.\n&quot;,
                                &quot;is_volatile&quot;: true,
                                &quot;access&quot;: &quot;read-write&quot;
                              }
                            }
                          }
                        }
                      }
                    }
                  }
                }
              }
            }"/>
          </xilinx:boundaryDescriptionInfo>
        </xilinx:componentInstanceExtensions>
      </spirit:vendorExtensions>
    </spirit:componentInstance>
  </spirit:componentInstances>
</spirit:design>
