!SESSION 2023-05-17 14:17:09.576 -----------------------------------------------
eclipse.buildId=2021.2
java.version=11.0.11
java.vendor=Oracle Corporation
BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=en_US
Command-line arguments:  -os linux -ws gtk -arch x86_64

!ENTRY org.eclipse.osgi 4 0 2023-05-17 14:17:09.861
!MESSAGE Bundle reference:file:org.apache.log4j_1.2.15.v201012070815.jar not found.

!ENTRY org.eclipse.osgi 4 0 2023-05-17 14:17:09.871
!MESSAGE Bundle reference:file:org.slf4j.impl.log4j12_1.7.2.v20131105-2200.jar not found.

!ENTRY org.eclipse.ui 4 4 2023-05-17 14:17:20.447
!MESSAGE Plug-in 'org.eclipse.ui.editors' contributed an invalid Menu Extension (Path: 'navigate' is invalid): org.eclipse.ui.edit.text.gotoLastEditPosition

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:22.778
!MESSAGE XSCT Command: [set sdk::sdk_chan tcfchan#0], Thread: Thread-19

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:22.778
!MESSAGE XSCT Command: [::hsi::utils::init_repo], Thread: Worker-2: Initializing s/w repositories

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:22.778
!MESSAGE XSCT Command: [plnx-install-path  ; ::scw::scw_mode gui], Thread: Thread-20

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:22.781
!MESSAGE XSCT command with result: [set sdk::sdk_chan tcfchan#0], Result: [null, tcfchan#0]. Thread: Thread-19

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:22.781
!MESSAGE XSCT command with result: [plnx-install-path  ; ::scw::scw_mode gui], Result: [null, ]. Thread: Thread-20

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:22.781
!MESSAGE XSCT Command: [setws /home/macro_fae/work/bmti/mb_max/mb_max.vs], Thread: Thread-19

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:22.808
!MESSAGE XSCT command with result: [::hsi::utils::init_repo], Result: [null, ]. Thread: Worker-2: Initializing s/w repositories

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:22.808
!MESSAGE XSCT command with result: [setws /home/macro_fae/work/bmti/mb_max/mb_max.vs], Result: [null, ]. Thread: Thread-19

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:22.809
!MESSAGE XSCT Command: [set query_var1 $::env(RDI_DATADIR)], Thread: Worker-2: Initializing s/w repositories

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:22.810
!MESSAGE XSCT command with result: [set query_var1 $::env(RDI_DATADIR)], Result: [null, /opt/Xilinx/Vitis/2022.1/data]. Thread: Worker-2: Initializing s/w repositories

!ENTRY com.xilinx.sdk.utils 1 0 2023-05-17 14:17:29.308
!MESSAGE Opening file dialog using preferences. Current path: /opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/fixed_hwplatforms, Local preference: scw_hwspec, Group preference: null

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:44.884
!MESSAGE XSCT Command: [::hsi::utils::openhw /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:45.157
!MESSAGE XSCT command with result: [::hsi::utils::openhw /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa], Result: [null, ]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:45.160
!MESSAGE XSCT Command: [::hsi::utils::get_design_properties -json /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:45.163
!MESSAGE XSCT command with result: [::hsi::utils::get_design_properties -json /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa], Result: [null, {"device": "7k325t",
"family": "kintex7",
"timestamp": "Thu Apr 20 17:32:43 2023",
"vivado_version": "2022.1",
"part": "xc7k325tffv676-1",
}]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:45.164
!MESSAGE XSCT Command: [::hsi::utils::get_all_periphs -json /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:45.167
!MESSAGE XSCT command with result: [::hsi::utils::get_all_periphs -json /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa], Result: [null, {"axi_timer_0": {"hier_name": "axi_timer_0",
"type": "axi_timer",
"version": "2.0",
"ip_type": "PERIPHERAL",
},
"axi_uartlite_0": {"hier_name": "axi_uartlite_0",
"type": "axi_uartlite",
"version": "2.0",
"ip_type": "PERIPHERAL",
},
"clk_wiz_0": {"hier_name": "clk_wiz_0",
"type": "clk_wiz",
"version": "6.0",
"ip_type": "PERIPHERAL",
},
"mdm_1": {"hier_name": "mdm_1",
"type": "mdm",
"version": "3.2",
"ip_type": "DEBUG",
},
"microblaze_0": {"hier_name": "microblaze_0",
"type": "microblaze",
"version": "11.0",
"ip_type": "PROCESSOR",
},
"microblaze_0_axi_intc": {"hier_name": "microblaze_0_axi_intc",
"type": "axi_intc",
"version": "4.1",
"ip_type": "INTERRUPT_CNTLR",
},
"microblaze_0_axi_periph": {"hier_name": "microblaze_0_axi_periph",
"type": "axi_interconnect",
"version": "2.1",
"ip_type": "BUS",
},
"microblaze_0_local_memory_dlmb_bram_if_cntlr": {"hier_name": "microblaze_0_local_memory_dlmb_bram_if_cntlr",
"type": "lmb_bram_if_cntlr",
"version": "4.0",
"ip_type": "MEMORY_CNTLR",
},
"microblaze_0_local_memory_dlmb_v10": {"hier_name": "microblaze_0_local_memory_dlmb_v10",
"type": "lmb_v10",
"version": "3.0",
"ip_type": "BUS",
},
"microblaze_0_local_memory_ilmb_bram_if_cntlr": {"hier_name": "microblaze_0_local_memory_ilmb_bram_if_cntlr",
"type": "lmb_bram_if_cntlr",
"version": "4.0",
"ip_type": "MEMORY_CNTLR",
},
"microblaze_0_local_memory_ilmb_v10": {"hier_name": "microblaze_0_local_memory_ilmb_v10",
"type": "lmb_v10",
"version": "3.0",
"ip_type": "BUS",
},
"microblaze_0_local_memory_lmb_bram": {"hier_name": "microblaze_0_local_memory_lmb_bram",
"type": "blk_mem_gen",
"version": "8.4",
"ip_type": "MEMORY",
},
"microblaze_0_xlconcat": {"hier_name": "microblaze_0_xlconcat",
"type": "xlconcat",
"version": "2.1",
"ip_type": "PERIPHERAL",
},
"mig_7series_0": {"hier_name": "mig_7series_0",
"type": "mig_7series",
"version": "4.2",
"ip_type": "MEMORY_CNTLR",
},
"rst_mig_7series_0_100M_1": {"hier_name": "rst_mig_7series_0_100M_1",
"type": "proc_sys_reset",
"version": "5.0",
"ip_type": "PERIPHERAL",
},
"smartconnect_0": {"hier_name": "smartconnect_0",
"type": "smartconnect",
"version": "1.0",
"ip_type": "BUS",
},
"util_ds_buf_1": {"hier_name": "util_ds_buf_1",
"type": "util_ds_buf",
"version": "2.2",
"ip_type": "PERIPHERAL",
},
"util_ds_buf_2": {"hier_name": "util_ds_buf_2",
"type": "util_ds_buf",
"version": "2.2",
"ip_type": "PERIPHERAL",
},
}]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:54.305
!MESSAGE XSCT Command: [hsi::utils::get_supported_os -json /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:54.308
!MESSAGE XSCT command with result: [hsi::utils::get_supported_os -json /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa], Result: [null, {"microblaze_0": {"freertos10_xilinx_v1_11": {"name": "freertos10_xilinx",
"version": "1.11",
"desc": "This Xilinx FreeRTOS port is based on FreeRTOS kernel version 10.4.6",
"compilerflags": "",
"linkerflags": "-Wl,--start-group,-lxil,-lfreertos,-lgcc,-lc,--end-group",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/ThirdParty/bsp/freertos10_xilinx_v1_11",
},
"standalone_v7_7": {"name": "standalone",
"version": "7.7",
"desc": "Standalone is a simple, low-level software layer. It provides access to basic processor features such as caches, interrupts and exceptions as well as the basic features of a hosted environment, such as standard input and output, profiling, abort and exit.",
"compilerflags": "",
"linkerflags": "-Wl,--start-group,-lxil,-lgcc,-lc,--end-group",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/bsp/standalone_v7_7",
},
},
}]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:54.310
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa microblaze_0 C_DATA_SIZE], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:54.312
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa microblaze_0 C_DATA_SIZE], Result: [null, 32]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:56.975
!MESSAGE XSCT Command: [::hsi::utils::get_all_app_details -json], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:56.981
!MESSAGE XSCT command with result: [::hsi::utils::get_all_app_details -json], Result: [null, {"srec_spi_bootloader": {"userdefname": "SREC SPI Bootloader",
"description": "Simple bootloader for loading SREC images from non volatile memory (SPI). This program assumes that you have an SREC image programmed into SPI flash already. The program also assumes that the target SREC image is an application for this processor that does not overlap the bootloader and resides in separate physical memory in the hardware. Typically this application is initialized into BRAM so that it bootloads the SREC image when the FPGA is powered up.

Don't forget to modify blconfig.h to reflect the offset where your SREC image resides in non-volatile memory!",
"supp_proc": "microblaze",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/srec_spi_bootloader",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"rsa_auth_app": {"userdefname": "RSA Authentication App",
"description": "Used to RSA authenticate a user application",
"supp_proc": "ps7_cortexa9",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/rsa_auth_app",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"versal_plm": {"userdefname": "versal PLM",
"description": "Platform Loader and Manager for versal.",
"supp_proc": "psu_pmc psv_pmc",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/versal_plm",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"zynq_fsbl": {"userdefname": "Zynq FSBL",
"description": "First Stage Bootloader (FSBL) for Zynq. The FSBL configures the FPGA with HW bit stream (if it exists)  and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the  non-volatile memory (NAND/NOR/QSPI) to RAM (DDR) and starts executing it.  It supports multiple partitions,  and each partition can be a code image or a bit stream.",
"supp_proc": "ps7_cortexa9",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/zynq_fsbl",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"openamp_matrix_multiply": {"userdefname": "OpenAMP matrix multiplication Demo",
"description": " OpenAMP matrix multiplication application ",
"supp_proc": "psu_cortexr5 psv_cortexr5 ps7_cortexa9",
"supp_os": "freertos10_xilinx standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/openamp_matrix_multiply",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"lwip_tcp_perf_server": {"userdefname": "lwIP TCP Perf Server",
"description": "The LwIP TCP Perf Server application is used for creating TCP server and measure downlink performance using light-weight IP stack (lwIP). This application sets up the board to use default IPv4 address 192.168.1.10 and IPv6 link local address when ipv6_enable is true, with MAC address 00:0a:35:00:01:02. The application creates TCP server on board and starts listening for TCP client connections. It will display client connection information with interim and average TCP statistics for data transfer.",
"supp_proc": "psv_cortexa72 psv_cortexr5 psu_cortexa53 psu_cortexr5 ps7_cortexa9 microblaze",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/lwip_tcp_perf_server",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"openamp_echo_test": {"userdefname": "OpenAMP echo-test",
"description": " OpenAMP echo-test application ",
"supp_proc": "psu_cortexr5 psv_cortexr5 ps7_cortexa9",
"supp_os": "freertos10_xilinx standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/openamp_echo_test",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"hello_world": {"userdefname": "Hello World",
"description": "Let's say 'Hello World' in C.",
"supp_proc": "microblaze ps7_cortexa9 psu_cortexa53 psu_cortexr5 psu_cortexa72 psv_cortexr5 psv_cortexa72",
"supp_os": "standalone xilkernel",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/hello_world",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "false",
},
"lwip_udp_perf_server": {"userdefname": "lwIP UDP Perf Server",
"description": "The LwIP UDP Perf Server application is used for creating UDP server and measure downlink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10, with MAC address 00:0a:35:00:01:02. The application creates UDP server on board and starts listening for UDP client connections. It will display client connection information with interim and average UDP statistics for data transfer.",
"supp_proc": "psv_cortexa72 psv_cortexr5 psu_cortexa53 psu_cortexr5 ps7_cortexa9 microblaze",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/lwip_udp_perf_server",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"lwip_echo_server": {"userdefname": "lwIP Echo Server",
"description": "The lwIP Echo Server application provides a simple demonstration of how to use the light-weight IP stack (lwIP). This application sets up the board to use IP address 192.168.1.10 or IPv6 FE80:0:0:0:20A:35FF:FE00:102, with MAC address 00:0a:35:00:01:02. The server listens for input at port 7 and simply echoes back whatever data is sent to that port.",
"supp_proc": "psv_cortexa72 psv_cortexr5 psu_cortexa53 psu_cortexr5 ps7_cortexa9 microblaze",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/lwip_echo_server",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"versal_psmfw": {"userdefname": "versal PSM Firmware",
"description": "Processing System Management Unit Firmware for versal.",
"supp_proc": "psu_psm psv_psm",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/versal_psmfw",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"zynqmp_fsbl": {"userdefname": "Zynq MP FSBL",
"description": "First Stage Bootloader (FSBL) for Zynq Ultrascale+ MPSoC. The FSBL configures the FPGA with HW bit stream (if it exists)  and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the  non-volatile memory (NAND/SD/QSPI) to RAM (DDR) and takes A53/R5 out of reset.  It supports multiple partitions,  and each partition can be a code image or a bit stream.",
"supp_proc": "psu_cortexa53 psu_cortexr5",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/zynqmp_fsbl",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"peripheral_tests": {"userdefname": "Peripheral Tests",
"description": "Simple test routines for all peripherals in the hardware.",
"supp_proc": "ps7_cortexa9 psu_cortexa53 psu_cortexr5 microblaze psv_cortexa72 psv_cortexr5",
"supp_os": "standalone xilkernel",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/peripheral_tests",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "false",
},
"dhrystone": {"userdefname": "Dhrystone",
"description": "Dhrystone synthetic benchmark program for baremetal environment.",
"supp_proc": "microblaze psu_cortexa53 ps7_cortexa9 psv_cortexa72 psu_cortexr5 psv_cortexr5",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/dhrystone",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "false",
},
"libmetal_echo_demo": {"userdefname": "Libmetal AMP Demo",
"description": "Libmetal AMP Application",
"supp_proc": "psu_cortexr5 psv_cortexr5",
"supp_os": "freertos10_xilinx standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/libmetal_echo_demo",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"freertos_lwip_udp_perf_server": {"userdefname": "FreeRTOS lwIP UDP Perf Server",
"description": "The FreeRTOS LwIP UDP Perf Server application is used for creating UDP server and measure downlink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10, with MAC address 00:0a:35:00:01:02. The application creates UDP server on board and starts listening for UDP client connections. It will display client connection information with interim and average UDP statistics for data transfer.",
"supp_proc": "psv_cortexa72 psv_cortexr5 psu_cortexa53 psu_cortexr5 ps7_cortexa9 microblaze",
"supp_os": "freertos10_xilinx",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/freertos_lwip_udp_perf_server",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"lwip_udp_perf_client": {"userdefname": "lwIP UDP Perf Client",
"description": "The LwIP UDP Perf Client application is used for creating UDP client and measure UDP uplink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10, with MAC address 00:0a:35:00:01:02. This application creates UDP client on board and make connection with UDP server running on host machine. It will display connection information along with interim and average UDP statistics for data transfer.",
"supp_proc": "psv_cortexa72 psv_cortexr5 psu_cortexa53 psu_cortexr5 ps7_cortexa9 microblaze",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/lwip_udp_perf_client",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"zynqmp_dram_test": {"userdefname": "Zynq MP DRAM tests",
"description": "This application runs out of OCM and performs memory tests on Zynq MP DRAM.  For more information about the test, refer to ZYNQMP_DRAM_DIAGNOSTICS_TEST.docx, in the src directory of the application",
"supp_proc": "psu_cortexa53",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/zynqmp_dram_test",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "false",
},
"memory_tests": {"userdefname": "Memory Tests",
"description": "This application tests Memory Regions present in the hardware.",
"supp_proc": "microblaze ps7_cortexa9 psu_cortexa53 psu_cortexr5 psv_cortexa72 psv_cortexr5",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/memory_tests",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "false",
},
"openamp_rpc_demo": {"userdefname": "OpenAMP RPC Demo",
"description": " OpenAMP rpc-demo application ",
"supp_proc": "psu_cortexr5 psv_cortexr5 ps7_cortexa9",
"supp_os": "freertos10_xilinx standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/openamp_rpc_demo",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"empty_application": {"userdefname": "Empty Application(C)",
"description": "A blank C project.",
"supp_proc": "microblaze ps7_cortexa9 psu_cortexa53 psu_cortexr5 psu_cortexa72 psv_cortexr5 psv_cortexa72",
"supp_os": "standalone xilkernel freertos10_xilinx",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/empty_application",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "false",
},
"freertos_lwip_echo_server": {"userdefname": "FreeRTOS lwIP Echo Server",
"description": "The FreeRTOS lwIP Echo Server application provides a simple demonstration of how to use the light-weight IP stack (lwIP) with FreeRTOS. This application sets up the board to use IP address 192.168.1.10 or IPv6 address FE80:0:0:0:20A:35FF:FE00:102, with MAC address 00:0a:35:00:01:02. The server listens for input at port 7 and simply echoes back whatever data is sent to that port.",
"supp_proc": "psv_cortexa72 psv_cortexr5 psu_cortexa53 psu_cortexr5 ps7_cortexa9 microblaze",
"supp_os": "freertos10_xilinx",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/freertos_lwip_echo_server",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"zynq_dram_test": {"userdefname": "Zynq DRAM tests",
"description": "This application runs out of OCM and performs memory tests and read/write eye measurements on Zynq DRAM.  For more information about the test, refer to ZYNQ_DRAM_DIAGNOSTICS_TEST.docx, in the src directory of the application",
"supp_proc": "ps7_cortexa9",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/zynq_dram_test",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "false",
},
"srec_bootloader": {"userdefname": "SREC Bootloader",
"description": "Simple bootloader for loading SREC images from non volatile memory. This program assumes that you have an SREC image programmed into BPI flash. The program also assumes that the target SREC image is an application for this processor that does not overlap the bootloader and resides in separate physical memory in the hardware. Typically this application is initialized into BRAM so that it bootloads the SREC image when the FPGA is powered up.

Don't forget to modify blconfig.h to reflect the physical address where your SREC image resides in non-volatile memory!",
"supp_proc": "microblaze",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/srec_bootloader",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "false",
},
"img_rcvry": {"userdefname": "Image Recovery",
"description": "Image Recovery tool which writes  user selected images on the board.",
"supp_proc": "psu_cortexa53",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/img_rcvry",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"mba_fs_boot": {"userdefname": "mba_fs_boot",
"description": "fs-boot for microblaze by Xilinx Inc..",
"supp_proc": "microblaze",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/mba_fs_boot",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"freertos_lwip_tcp_perf_server": {"userdefname": "FreeRTOS lwIP TCP Perf Server",
"description": "The FreeRTOS LwIP TCP Server application is used for creating TCP server using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10 and IPv6 link local address when ipv6_enable is true, with MAC address 00:0a:35:00:01:02. The application creates TCP server on board and starts listening for TCP client connections. It will display client connection info and also display interim and average TCP statistics for data transfer. This application handles only 1 client connection at a time.",
"supp_proc": "psv_cortexa72 psv_cortexr5 psu_cortexa53 psu_cortexr5 ps7_cortexa9 microblaze",
"supp_os": "freertos10_xilinx",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/freertos_lwip_tcp_perf_server",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"freertos_lwip_udp_perf_client": {"userdefname": "FreeRTOS lwIP UDP Perf Client",
"description": "The FreeRTOS LwIP UDP Perf Client application is used for creating UDP client and measure UDP uplink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10, with MAC address 00:0a:35:00:01:02. This application creates UDP client on board and make connection with UDP server running on host machine. It will display connection information along with interim and average UDP statistics for data transfer.",
"supp_proc": "psv_cortexa72 psv_cortexr5 psu_cortexa53 psu_cortexr5 ps7_cortexa9 microblaze",
"supp_os": "freertos10_xilinx",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/freertos_lwip_udp_perf_client",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"ddr_self_refresh": {"userdefname": "DDR self refresh",
"description": "This DDR self refresh application provides a simple demonstration of how to enter to/exit from DDR self refresh mode. This application runs on R5 out of TCM.",
"supp_proc": "psu_cortexr5",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/ddr_self_refresh",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"freertos_lwip_tcp_perf_client": {"userdefname": "FreeRTOS lwIP TCP Perf Client",
"description": "The FreeRTOS LwIP TCP Perf Client application is used for creating TCP client and measure TCP uplink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10 and IPv6 link local address whenipv6_enable is true, with MAC address 00:0a:35:00:01:02. This application creates TCP client on board and make connection with TCP server running on host machine. It will display connection information along with interim and average TCP statistics for data transfer.",
"supp_proc": "psv_cortexa72 psv_cortexr5 psu_cortexa53 psu_cortexr5 ps7_cortexa9 microblaze",
"supp_os": "freertos10_xilinx",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/freertos_lwip_tcp_perf_client",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"lwip_tcp_perf_client": {"userdefname": "lwIP TCP Perf Client",
"description": "The LwIP TCP Perf Client application is used for creating TCP client and measure TCP uplink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10 and IPv6 link local address when ipv6_enable is true, with MAC address 00:0a:35:00:01:02. This application creates TCP client on board and make connection with TCP server running on host machine. It will display connection information along with interim and average TCP statistics for data transfer.",
"supp_proc": "psv_cortexa72 psv_cortexr5 psu_cortexa53 psu_cortexr5 ps7_cortexa9 microblaze",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/lwip_tcp_perf_client",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"imgsel": {"userdefname": "Image Selector",
"description": "ImgSel for Zynq Ultrascale+ MPSoC. The Image Selector  selects the image based on configuration parameters",
"supp_proc": "psu_cortexa53",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/imgsel",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"freertos_hello_world": {"userdefname": "FreeRTOS Hello World",
"description": " FreeRTOS Hello World application",
"supp_proc": "psu_cortexr5 psv_cortexr5 ps7_cortexa9 psu_cortexa53 microblaze psv_cortexa72",
"supp_os": "freertos10_xilinx",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/freertos_hello_world",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"zynqmp_pmufw": {"userdefname": "ZynqMP PMU Firmware",
"description": "Platform Management Unit Firmware for ZynqMP.",
"supp_proc": "psu_pmu",
"supp_os": "standalone",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps/zynqmp_pmufw",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "true",
},
"linux_hello_world": {"userdefname": "Linux Hello World",
"description": "Let's say 'Hello World' in C.",
"supp_proc": "ps7_cortexa9 psu_cortexa53 microblaze psv_cortexa72",
"supp_os": "linux",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps_linux/linux_hello_world",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "false",
},
"linux_empty_app": {"userdefname": "Linux Empty Application",
"description": "A blank Linux C project.",
"supp_proc": "ps7_cortexa9 psu_cortexa53 microblaze psv_cortexa72",
"supp_os": "linux",
"path": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/sw_apps_linux/linux_empty_app",
"os": "linux",
"platform_required": NO,
"bsp_constraints": "false",
},
}]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:57.011
!MESSAGE XSCT Command: [::hsi::utils::is_app_supported_on_hw_sw  -hw /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa -os standalone -processor microblaze_0 -app hello_world -sw {} -arch {}], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:57.016
!MESSAGE XSCT command with result: [::hsi::utils::is_app_supported_on_hw_sw  -hw /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa -os standalone -processor microblaze_0 -app hello_world -sw {} -arch {}], Result: [null, 1]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:57.016
!MESSAGE XSCT Command: [::hsi::utils::is_app_supported_on_hw_sw  -hw /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa -os standalone -processor microblaze_0 -app hello_world -sw {} -arch {}], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:57.021
!MESSAGE XSCT command with result: [::hsi::utils::is_app_supported_on_hw_sw  -hw /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa -os standalone -processor microblaze_0 -app hello_world -sw {} -arch {}], Result: [null, 1]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:59.568
!MESSAGE XSCT Command: [platform create -name {design_1_wrapper} -hw {/home/macro_fae/work/bmti/mb_max/design_1_wrapper.xsa} -out {/home/macro_fae/work/bmti/mb_max/mb_max.vs};platform write], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:59.899
!MESSAGE XSCT command with result: [platform create -name {design_1_wrapper} -hw {/home/macro_fae/work/bmti/mb_max/design_1_wrapper.xsa} -out {/home/macro_fae/work/bmti/mb_max/mb_max.vs};platform write], Result: [null, Successfully saved  the platform at "/home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/platform.spr"]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:17:59.902
!MESSAGE XSCT Command: [domain create -name {standalone_microblaze_0} -display-name {standalone_microblaze_0} -os {standalone} -proc {microblaze_0} -runtime {cpp} -arch {32-bit} -support-app {hello_world}], Thread: ModalContext

!ENTRY org.eclipse.e4.ui.workbench 4 0 2023-05-17 14:17:59.914
!MESSAGE 
!STACK 0
java.lang.NullPointerException
	at org.eclipse.ui.part.IntroPart.dispose(IntroPart.java:99)
	at org.eclipse.ui.internal.ViewIntroAdapterPart.dispose(ViewIntroAdapterPart.java:153)
	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.invalidate(CompatibilityPart.java:260)
	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.destroy(CompatibilityPart.java:417)
	at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
	at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
	at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
	at java.base/java.lang.reflect.Method.invoke(Method.java:566)
	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:58)
	at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:1002)
	at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:967)
	at org.eclipse.e4.core.internal.di.InjectorImpl.uninject(InjectorImpl.java:200)
	at org.eclipse.e4.core.internal.di.Requestor.uninject(Requestor.java:176)
	at org.eclipse.e4.core.internal.contexts.ContextObjectSupplier$ContextInjectionListener.update(ContextObjectSupplier.java:89)
	at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.update(TrackableComputationExt.java:105)
	at org.eclipse.e4.core.internal.contexts.EclipseContext.removeListenersTo(EclipseContext.java:491)
	at org.eclipse.e4.core.contexts.ContextInjectionFactory.uninject(ContextInjectionFactory.java:184)
	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeRemoveGui(PartRenderingEngine.java:954)
	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$1(PartRenderingEngine.java:873)
	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$4.run(PartRenderingEngine.java:868)
	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:45)
	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.removeGui(PartRenderingEngine.java:852)
	at org.eclipse.e4.ui.workbench.renderers.swt.ElementReferenceRenderer.disposeWidget(ElementReferenceRenderer.java:115)
	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeRemoveGui(PartRenderingEngine.java:945)
	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$1(PartRenderingEngine.java:873)
	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$4.run(PartRenderingEngine.java:868)
	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:45)
	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.removeGui(PartRenderingEngine.java:852)
	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.subscribeTopicToBeRendered(PartRenderingEngine.java:187)
	at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
	at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
	at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
	at java.base/java.lang.reflect.Method.invoke(Method.java:566)
	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:58)
	at org.eclipse.e4.core.di.internal.extensions.EventObjectSupplier$DIEventHandler.handleEvent(EventObjectSupplier.java:92)
	at org.eclipse.equinox.internal.event.EventHandlerWrapper.handleEvent(EventHandlerWrapper.java:205)
	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:203)
	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:1)
	at org.eclipse.osgi.framework.eventmgr.EventManager.dispatchEvent(EventManager.java:234)
	at org.eclipse.osgi.framework.eventmgr.ListenerQueue.dispatchEventSynchronous(ListenerQueue.java:151)
	at org.eclipse.equinox.internal.event.EventAdminImpl.dispatchEvent(EventAdminImpl.java:132)
	at org.eclipse.equinox.internal.event.EventAdminImpl.sendEvent(EventAdminImpl.java:75)
	at org.eclipse.equinox.internal.event.EventComponent.sendEvent(EventComponent.java:44)
	at org.eclipse.e4.ui.services.internal.events.EventBroker.send(EventBroker.java:55)
	at org.eclipse.e4.ui.internal.workbench.UIEventPublisher.notifyChanged(UIEventPublisher.java:63)
	at org.eclipse.emf.common.notify.impl.BasicNotifierImpl.eNotify(BasicNotifierImpl.java:424)
	at org.eclipse.e4.ui.model.application.ui.impl.UIElementImpl.setToBeRendered(UIElementImpl.java:314)
	at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1406)
	at org.eclipse.ui.internal.WorkbenchPage.hidePart(WorkbenchPage.java:1537)
	at org.eclipse.ui.internal.WorkbenchPage.hidePart(WorkbenchPage.java:1496)
	at org.eclipse.ui.internal.WorkbenchPage.hideView(WorkbenchPage.java:2609)
	at org.eclipse.ui.internal.WorkbenchIntroManager.closeIntro(WorkbenchIntroManager.java:98)
	at com.xilinx.sdx.ui.utils.SWTUtils.closeWelcomeView(SWTUtils.java:529)
	at com.xilinx.sdx.scw.project.ScwProjectCreationHandler$1.run(ScwProjectCreationHandler.java:71)
	at org.eclipse.swt.widgets.RunnableLock.run(RunnableLock.java:40)
	at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:185)
	at org.eclipse.swt.widgets.Display.runAsyncMessages(Display.java:4930)
	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:4451)
	at org.eclipse.jface.operation.ModalContext$ModalContextThread.block(ModalContext.java:166)
	at org.eclipse.jface.operation.ModalContext.run(ModalContext.java:368)
	at org.eclipse.jface.wizard.WizardDialog.run(WizardDialog.java:1033)
	at com.xilinx.sdx.npw.NewProjectCreationHandler.execute(NewProjectCreationHandler.java:105)
	at com.xilinx.sdx.npw.NewProjectWizard._createApplicationProject(NewProjectWizard.java:214)
	at com.xilinx.sdx.npw.NewProjectWizard.performFinish(NewProjectWizard.java:161)
	at org.eclipse.jface.wizard.WizardDialog.finishPressed(WizardDialog.java:832)
	at org.eclipse.jface.wizard.WizardDialog.buttonPressed(WizardDialog.java:472)
	at org.eclipse.jface.dialogs.Dialog.lambda$0(Dialog.java:619)
	at org.eclipse.swt.events.SelectionListener$1.widgetSelected(SelectionListener.java:84)
	at org.eclipse.swt.widgets.TypedListener.handleEvent(TypedListener.java:252)
	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:89)
	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:5687)
	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1423)
	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4955)
	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:4448)
	at org.eclipse.jface.window.Window.runEventLoop(Window.java:823)
	at org.eclipse.jface.window.Window.open(Window.java:799)
	at com.xilinx.sdx.npw.OpenApplicationProjectWizardAction.run(OpenApplicationProjectWizardAction.java:27)
	at com.xilinx.sdx.npw.OpenApplicationProjectWizardAction.clicked(OpenApplicationProjectWizardAction.java:44)
	at com.xilinx.ide.product.intro.IDEIntroPart.createApplicationProject(IDEIntroPart.java:475)
	at com.xilinx.ide.product.intro.IDEIntroPart$3.run(IDEIntroPart.java:274)
	at com.xilinx.ide.product.intro.IDEIntroPart$12.mouseUp(IDEIntroPart.java:402)
	at org.eclipse.swt.widgets.TypedListener.handleEvent(TypedListener.java:224)
	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:89)
	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:5687)
	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1423)
	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4955)
	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:4448)
	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$5.run(PartRenderingEngine.java:1160)
	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:338)
	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1049)
	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:155)
	at org.eclipse.ui.internal.Workbench.lambda$3(Workbench.java:658)
	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:338)
	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:557)
	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:154)
	at com.xilinx.ide.application.ui.Application.start(Application.java:80)
	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:137)
	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:107)
	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:401)
	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
	at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
	at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
	at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
	at java.base/java.lang.reflect.Method.invoke(Method.java:566)
	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:657)
	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:594)
	at org.eclipse.equinox.launcher.Main.run(Main.java:1447)
	at org.eclipse.equinox.launcher.Main.main(Main.java:1420)

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.102
!MESSAGE XSCT command with result: [domain create -name {standalone_microblaze_0} -display-name {standalone_microblaze_0} -os {standalone} -proc {microblaze_0} -runtime {cpp} -arch {32-bit} -support-app {hello_world}], Result: [null, ]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.104
!MESSAGE XSCT Command: [platform write], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.107
!MESSAGE XSCT command with result: [platform write], Result: [null, Successfully saved  the platform at "/home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/platform.spr"]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.113
!MESSAGE XSCT Command: [platform active {design_1_wrapper}], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.114
!MESSAGE XSCT command with result: [platform active {design_1_wrapper}], Result: [null, ]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.115
!MESSAGE XSCT Command: [platform generate -quick], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.119
!MESSAGE XSCT command with result: [platform generate -quick], Result: [null, Successfully generated platform at "/home/macro_fae/work/bmti/mb_max/mb_max.vs"]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.329
!MESSAGE XSCT Command: [::hsi::utils::openhw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.602
!MESSAGE XSCT command with result: [::hsi::utils::openhw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa], Result: [null, ]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.602
!MESSAGE XSCT Command: [::hsi::utils::get_all_periphs -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.605
!MESSAGE XSCT command with result: [::hsi::utils::get_all_periphs -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa], Result: [null, {"axi_timer_0": {"hier_name": "axi_timer_0",
"type": "axi_timer",
"version": "2.0",
"ip_type": "PERIPHERAL",
},
"axi_uartlite_0": {"hier_name": "axi_uartlite_0",
"type": "axi_uartlite",
"version": "2.0",
"ip_type": "PERIPHERAL",
},
"clk_wiz_0": {"hier_name": "clk_wiz_0",
"type": "clk_wiz",
"version": "6.0",
"ip_type": "PERIPHERAL",
},
"mdm_1": {"hier_name": "mdm_1",
"type": "mdm",
"version": "3.2",
"ip_type": "DEBUG",
},
"microblaze_0": {"hier_name": "microblaze_0",
"type": "microblaze",
"version": "11.0",
"ip_type": "PROCESSOR",
},
"microblaze_0_axi_intc": {"hier_name": "microblaze_0_axi_intc",
"type": "axi_intc",
"version": "4.1",
"ip_type": "INTERRUPT_CNTLR",
},
"microblaze_0_axi_periph": {"hier_name": "microblaze_0_axi_periph",
"type": "axi_interconnect",
"version": "2.1",
"ip_type": "BUS",
},
"microblaze_0_local_memory_dlmb_bram_if_cntlr": {"hier_name": "microblaze_0_local_memory_dlmb_bram_if_cntlr",
"type": "lmb_bram_if_cntlr",
"version": "4.0",
"ip_type": "MEMORY_CNTLR",
},
"microblaze_0_local_memory_dlmb_v10": {"hier_name": "microblaze_0_local_memory_dlmb_v10",
"type": "lmb_v10",
"version": "3.0",
"ip_type": "BUS",
},
"microblaze_0_local_memory_ilmb_bram_if_cntlr": {"hier_name": "microblaze_0_local_memory_ilmb_bram_if_cntlr",
"type": "lmb_bram_if_cntlr",
"version": "4.0",
"ip_type": "MEMORY_CNTLR",
},
"microblaze_0_local_memory_ilmb_v10": {"hier_name": "microblaze_0_local_memory_ilmb_v10",
"type": "lmb_v10",
"version": "3.0",
"ip_type": "BUS",
},
"microblaze_0_local_memory_lmb_bram": {"hier_name": "microblaze_0_local_memory_lmb_bram",
"type": "blk_mem_gen",
"version": "8.4",
"ip_type": "MEMORY",
},
"microblaze_0_xlconcat": {"hier_name": "microblaze_0_xlconcat",
"type": "xlconcat",
"version": "2.1",
"ip_type": "PERIPHERAL",
},
"mig_7series_0": {"hier_name": "mig_7series_0",
"type": "mig_7series",
"version": "4.2",
"ip_type": "MEMORY_CNTLR",
},
"rst_mig_7series_0_100M_1": {"hier_name": "rst_mig_7series_0_100M_1",
"type": "proc_sys_reset",
"version": "5.0",
"ip_type": "PERIPHERAL",
},
"smartconnect_0": {"hier_name": "smartconnect_0",
"type": "smartconnect",
"version": "1.0",
"ip_type": "BUS",
},
"util_ds_buf_1": {"hier_name": "util_ds_buf_1",
"type": "util_ds_buf",
"version": "2.2",
"ip_type": "PERIPHERAL",
},
"util_ds_buf_2": {"hier_name": "util_ds_buf_2",
"type": "util_ds_buf",
"version": "2.2",
"ip_type": "PERIPHERAL",
},
}]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.616
!MESSAGE XSCT Command: [ ::hsi::utils::set_current_hw_sw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss ], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.618
!MESSAGE XSCT command with result: [ ::hsi::utils::set_current_hw_sw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss ], Result: [null, ]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.619
!MESSAGE XSCT Command: [::hsi::utils::get_hw_sw_details -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.620
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_sw_details -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Result: [null, {"procname": "microblaze_0",
"osname": "standalone",
"osver": "7.7",
}]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.924
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_USE_REORDER_INSTR], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.925
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_USE_REORDER_INSTR], Result: [null, 1]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.926
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_ENDIANNESS], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.927
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_ENDIANNESS], Result: [null, 1]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.927
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_USE_BARREL], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.928
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_USE_BARREL], Result: [null, 1]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.929
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_USE_PCMP_INSTR], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.929
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_USE_PCMP_INSTR], Result: [null, 1]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.930
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_USE_DIV], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.931
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_USE_DIV], Result: [null, 1]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.931
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_USE_FPU], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.932
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_USE_FPU], Result: [null, 1]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.932
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_USE_HW_MUL], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.933
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_USE_HW_MUL], Result: [null, 2]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.933
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_AREA_OPTIMIZED], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.934
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0 C_AREA_OPTIMIZED], Result: [null, 0]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.936
!MESSAGE XSCT Command: [hsi::utils::get_supported_os -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.940
!MESSAGE XSCT command with result: [hsi::utils::get_supported_os -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa], Result: [null, {"microblaze_0": {"freertos10_xilinx_v1_11": {"name": "freertos10_xilinx",
"version": "1.11",
"desc": "This Xilinx FreeRTOS port is based on FreeRTOS kernel version 10.4.6",
"compilerflags": "",
"linkerflags": "-Wl,--start-group,-lxil,-lfreertos,-lgcc,-lc,--end-group",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/ThirdParty/bsp/freertos10_xilinx_v1_11",
},
"standalone_v7_7": {"name": "standalone",
"version": "7.7",
"desc": "Standalone is a simple, low-level software layer. It provides access to basic processor features such as caches, interrupts and exceptions as well as the basic features of a hosted environment, such as standard input and output, profiling, abort and exit.",
"compilerflags": "",
"linkerflags": "-Wl,--start-group,-lxil,-lgcc,-lc,--end-group",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/bsp/standalone_v7_7",
},
},
}]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.940
!MESSAGE XSCT Command: [::hsi::utils::get_libs_from_sw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.941
!MESSAGE XSCT command with result: [::hsi::utils::get_libs_from_sw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Result: [null, ]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.942
!MESSAGE XSCT Command: [::hsi::utils::get_sw_libs -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.942
!MESSAGE XSCT command with result: [::hsi::utils::get_sw_libs -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Result: [null, {}]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.943
!MESSAGE XSCT Command: [::hsi::utils::get_connected_periphs /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.943
!MESSAGE XSCT command with result: [::hsi::utils::get_connected_periphs /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0], Result: [null, axi_timer_0 axi_uartlite_0 microblaze_0_axi_intc microblaze_0_local_memory_dlmb_bram_if_cntlr microblaze_0_local_memory_ilmb_bram_if_cntlr mig_7series_0]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.944
!MESSAGE XSCT Command: [::hsi::utils::get_drivers_for_sw -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.945
!MESSAGE XSCT command with result: [::hsi::utils::get_drivers_for_sw -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Result: [null, {"axi_timer_0": {"name": "tmrctr",
"ver": "4.9",
},
"axi_uartlite_0": {"name": "uartlite",
"ver": "3.7",
},
"microblaze_0_axi_intc": {"name": "intc",
"ver": "3.14",
},
"microblaze_0_local_memory_dlmb_bram_if_cntlr": {"name": "bram",
"ver": "4.7",
},
"microblaze_0_local_memory_ilmb_bram_if_cntlr": {"name": "bram",
"ver": "4.7",
},
"mig_7series_0": {"name": "mig_7series",
"ver": "2.2",
},
"microblaze_0": {"name": "cpu",
"ver": "2.15",
},
}]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.945
!MESSAGE XSCT Command: [hsi::utils::get_drivers_for_hw -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.972
!MESSAGE XSCT command with result: [hsi::utils::get_drivers_for_hw -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa], Result: [null, {"axi_timer_0": {"version": "2.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"tmrctr_v4_9": {"name": "tmrctr",
"version": "4.9",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/tmrctr_v4_9",
"compilerflags": "",
"linkerflags": "",
},
},
},
"axi_uartlite_0": {"version": "2.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"uartlite_v3_7": {"name": "uartlite",
"version": "3.7",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_7",
"compilerflags": "",
"linkerflags": "",
},
},
},
"clk_wiz_0": {"version": "6.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"clk_wiz_v1_4": {"name": "clk_wiz",
"version": "1.4",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/clk_wiz_v1_4",
"compilerflags": "",
"linkerflags": "",
},
},
},
"mdm_1": {"version": "3.2",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"uartlite_v3_7": {"name": "uartlite",
"version": "3.7",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_7",
"compilerflags": "",
"linkerflags": "",
},
},
},
"microblaze_0": {"version": "11.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"cpu_v2_15": {"name": "cpu",
"version": "2.15",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/cpu_v2_15",
"compilerflags": "",
"linkerflags": "",
},
},
},
"microblaze_0_axi_intc": {"version": "4.1",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"intc_v3_14": {"name": "intc",
"version": "3.14",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/intc_v3_14",
"compilerflags": "",
"linkerflags": "",
},
},
},
"microblaze_0_axi_periph": {"version": "2.1",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"microblaze_0_local_memory_dlmb_bram_if_cntlr": {"version": "4.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"bram_v4_7": {"name": "bram",
"version": "4.7",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/bram_v4_7",
"compilerflags": "",
"linkerflags": "",
},
},
},
"microblaze_0_local_memory_dlmb_v10": {"version": "3.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"microblaze_0_local_memory_ilmb_bram_if_cntlr": {"version": "4.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"bram_v4_7": {"name": "bram",
"version": "4.7",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/bram_v4_7",
"compilerflags": "",
"linkerflags": "",
},
},
},
"microblaze_0_local_memory_ilmb_v10": {"version": "3.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"microblaze_0_local_memory_lmb_bram": {"version": "8.4",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"microblaze_0_xlconcat": {"version": "2.1",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"mig_7series_0": {"version": "4.2",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"mig_7series_v2_2": {"name": "mig_7series",
"version": "2.2",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/mig_7series_v2_2",
"compilerflags": "",
"linkerflags": "",
},
},
},
"rst_mig_7series_0_100M_1": {"version": "5.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"smartconnect_0": {"version": "1.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"util_ds_buf_1": {"version": "2.2",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"util_ds_buf_2": {"version": "2.2",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
}]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.974
!MESSAGE XSCT Command: [::hsi::utils::get_libs_from_sw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.975
!MESSAGE XSCT command with result: [::hsi::utils::get_libs_from_sw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Result: [null, ]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.975
!MESSAGE XSCT Command: [::hsi::utils::get_sw_libs -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.976
!MESSAGE XSCT command with result: [::hsi::utils::get_sw_libs -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Result: [null, {}]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.994
!MESSAGE XSCT Command: [::hsi::utils::openhw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.995
!MESSAGE XSCT command with result: [::hsi::utils::openhw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa], Result: [null, ]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.995
!MESSAGE XSCT Command: [::hsi::utils::opensw /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.995
!MESSAGE XSCT command with result: [::hsi::utils::opensw /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Result: [null, ]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:00.996
!MESSAGE XSCT Command: [::hsi::utils::generate_app_template -hw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa -sw /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss -app hello_world -processor microblaze_0 -os standalone -dir /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/src], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:01.013
!MESSAGE XSCT command with result: [::hsi::utils::generate_app_template -hw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa -sw /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss -app hello_world -processor microblaze_0 -os standalone -dir /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/src], Result: [null, ]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:01.038
!MESSAGE XSCT Command: [hsi::internal::extract_hw_files -quiet bit mmi bmm -dir {/home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/_ide/bitstream}], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:01.067
!MESSAGE XSCT command with result: [hsi::internal::extract_hw_files -quiet bit mmi bmm -dir {/home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/_ide/bitstream}], Result: [null, ]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:01.067
!MESSAGE XSCT Command: [::hsi::utils::get_design_properties -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:01.068
!MESSAGE XSCT command with result: [::hsi::utils::get_design_properties -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa], Result: [null, {"device": "7k325t",
"family": "kintex7",
"timestamp": "Thu Apr 20 17:32:43 2023",
"vivado_version": "2022.1",
"part": "xc7k325tffv676-1",
}]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:01.109
!MESSAGE XSCT Command: [::hsi::utils::closesw /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:01.110
!MESSAGE XSCT command with result: [::hsi::utils::closesw /home/macro_fae/work/bmti/mb_max/mb_max.vs/hello/system.mss], Result: [null, ]. Thread: ModalContext

!ENTRY com.xilinx.sdk.utils 1 0 2023-05-17 14:18:01.128
!MESSAGE Generating MD5 hash for file: /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/export/design_1_wrapper/sw/design_1_wrapper/standalone_microblaze_0/system.mss ...

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:01.413
!MESSAGE XSCT Command: [::hsi::utils::closehw /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:01.416
!MESSAGE XSCT command with result: [::hsi::utils::closehw /tmp/hwspec_design_1_wrapper4915230780444226834/design_1_wrapper.xsa], Result: [null, ]. Thread: main

!ENTRY org.eclipse.launchbar.core 2 0 2023-05-17 14:18:01.533
!MESSAGE Enablement expression is missing for descriptor type org.eclipse.cdt.debug.core.coreBuildDescriptorType

!ENTRY org.eclipse.launchbar.core 2 0 2023-05-17 14:18:01.534
!MESSAGE Enablement expression is missing for config provider for org.eclipse.cdt.debug.core.coreBuildDescriptorType

!ENTRY org.eclipse.launchbar.core 2 0 2023-05-17 14:18:01.534
!MESSAGE Enablement expression is missing for config provider for org.eclipse.cdt.debug.core.coreBuildDescriptorType

!ENTRY org.eclipse.cdt.core 1 0 2023-05-17 14:18:01.831
!MESSAGE Indexed 'hello' (2 sources, 52 headers) in 0.316 sec: 1,538 declarations; 2,228 references; 0 unresolved inclusions; 0 syntax errors; 0 unresolved names (0%)

!ENTRY org.eclipse.cdt.core 1 0 2023-05-17 14:18:01.833
!MESSAGE Indexed 'hello_system' (0 sources, 0 headers) in 0 sec: 0 declarations; 0 references; 0 unresolved inclusions; 0 syntax errors; 0 unresolved names (0%)

!ENTRY org.eclipse.cdt.core 1 0 2023-05-17 14:18:03.195
!MESSAGE Indexed 'design_1_wrapper' (166 sources, 173 headers) in 1.35 sec: 4,695 declarations; 18,940 references; 87 unresolved inclusions; 40 syntax errors; 287 unresolved names (1.2%)

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:49.647
!MESSAGE XSCT Command: [platform read {/home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/platform.spr}], Thread: Worker-5: Initializing the platform to enable editing

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:49.650
!MESSAGE XSCT Command: [::hsi::utils::openhw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa], Thread: Worker-2: Initializing hardware specification UI...

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:49.981
!MESSAGE XSCT command with result: [platform read {/home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/platform.spr}], Result: [null, ]. Thread: Worker-5: Initializing the platform to enable editing

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:49.982
!MESSAGE XSCT command with result: [::hsi::utils::openhw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa], Result: [null, ]. Thread: Worker-2: Initializing hardware specification UI...

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.754
!MESSAGE XSCT Command: [::scw::get_hw_path], Thread: Worker-7: Initializing 'standalone_microblaze_0' bsp settings UI...

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.755
!MESSAGE XSCT command with result: [::scw::get_hw_path], Result: [null, /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa]. Thread: Worker-7: Initializing 'standalone_microblaze_0' bsp settings UI...

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.755
!MESSAGE XSCT Command: [::scw::regenerate_psinit /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa], Thread: Worker-7: Initializing 'standalone_microblaze_0' bsp settings UI...

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.756
!MESSAGE XSCT command with result: [::scw::regenerate_psinit /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa], Result: [null, ]. Thread: Worker-7: Initializing 'standalone_microblaze_0' bsp settings UI...

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.757
!MESSAGE XSCT Command: [::scw::get_mss_path], Thread: Worker-7: Initializing 'standalone_microblaze_0' bsp settings UI...

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.758
!MESSAGE XSCT command with result: [::scw::get_mss_path], Result: [null, /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/microblaze_0/standalone_microblaze_0/bsp/system.mss]. Thread: Worker-7: Initializing 'standalone_microblaze_0' bsp settings UI...

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.759
!MESSAGE XSCT Command: [ ::hsi::utils::set_current_hw_sw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/microblaze_0/standalone_microblaze_0/bsp/system.mss ], Thread: Worker-7: Initializing 'standalone_microblaze_0' bsp settings UI...

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.760
!MESSAGE XSCT command with result: [ ::hsi::utils::set_current_hw_sw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/microblaze_0/standalone_microblaze_0/bsp/system.mss ], Result: [null, ]. Thread: Worker-7: Initializing 'standalone_microblaze_0' bsp settings UI...

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.760
!MESSAGE XSCT Command: [::hsi::utils::get_hw_sw_details -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/microblaze_0/standalone_microblaze_0/bsp/system.mss], Thread: Worker-7: Initializing 'standalone_microblaze_0' bsp settings UI...

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.762
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_sw_details -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/microblaze_0/standalone_microblaze_0/bsp/system.mss], Result: [null, {"procname": "microblaze_0",
"osname": "standalone",
"osver": "7.7",
}]. Thread: Worker-7: Initializing 'standalone_microblaze_0' bsp settings UI...

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.774
!MESSAGE XSCT Command: [hsi::utils::get_supported_os -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.778
!MESSAGE XSCT command with result: [hsi::utils::get_supported_os -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa], Result: [null, {"microblaze_0": {"freertos10_xilinx_v1_11": {"name": "freertos10_xilinx",
"version": "1.11",
"desc": "This Xilinx FreeRTOS port is based on FreeRTOS kernel version 10.4.6",
"compilerflags": "",
"linkerflags": "-Wl,--start-group,-lxil,-lfreertos,-lgcc,-lc,--end-group",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/ThirdParty/bsp/freertos10_xilinx_v1_11",
},
"standalone_v7_7": {"name": "standalone",
"version": "7.7",
"desc": "Standalone is a simple, low-level software layer. It provides access to basic processor features such as caches, interrupts and exceptions as well as the basic features of a hosted environment, such as standard input and output, profiling, abort and exit.",
"compilerflags": "",
"linkerflags": "-Wl,--start-group,-lxil,-lgcc,-lc,--end-group",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/lib/bsp/standalone_v7_7",
},
},
}]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.791
!MESSAGE XSCT Command: [::hsi::utils::get_connected_periphs /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.792
!MESSAGE XSCT command with result: [::hsi::utils::get_connected_periphs /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0], Result: [null, axi_timer_0 axi_uartlite_0 microblaze_0_axi_intc microblaze_0_local_memory_dlmb_bram_if_cntlr microblaze_0_local_memory_ilmb_bram_if_cntlr mig_7series_0]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.792
!MESSAGE XSCT Command: [::hsi::utils::get_drivers_for_sw -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/microblaze_0/standalone_microblaze_0/bsp/system.mss], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.794
!MESSAGE XSCT command with result: [::hsi::utils::get_drivers_for_sw -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/microblaze_0/standalone_microblaze_0/bsp/system.mss], Result: [null, {"axi_timer_0": {"name": "tmrctr",
"ver": "4.9",
},
"axi_uartlite_0": {"name": "uartlite",
"ver": "3.7",
},
"microblaze_0_axi_intc": {"name": "intc",
"ver": "3.14",
},
"microblaze_0_local_memory_dlmb_bram_if_cntlr": {"name": "bram",
"ver": "4.7",
},
"microblaze_0_local_memory_ilmb_bram_if_cntlr": {"name": "bram",
"ver": "4.7",
},
"mig_7series_0": {"name": "mig_7series",
"ver": "2.2",
},
"microblaze_0": {"name": "cpu",
"ver": "2.15",
},
}]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.795
!MESSAGE XSCT Command: [hsi::utils::get_drivers_for_hw -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.820
!MESSAGE XSCT command with result: [hsi::utils::get_drivers_for_hw -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa], Result: [null, {"axi_timer_0": {"version": "2.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"tmrctr_v4_9": {"name": "tmrctr",
"version": "4.9",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/tmrctr_v4_9",
"compilerflags": "",
"linkerflags": "",
},
},
},
"axi_uartlite_0": {"version": "2.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"uartlite_v3_7": {"name": "uartlite",
"version": "3.7",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_7",
"compilerflags": "",
"linkerflags": "",
},
},
},
"clk_wiz_0": {"version": "6.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"clk_wiz_v1_4": {"name": "clk_wiz",
"version": "1.4",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/clk_wiz_v1_4",
"compilerflags": "",
"linkerflags": "",
},
},
},
"mdm_1": {"version": "3.2",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"uartlite_v3_7": {"name": "uartlite",
"version": "3.7",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_7",
"compilerflags": "",
"linkerflags": "",
},
},
},
"microblaze_0": {"version": "11.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"cpu_v2_15": {"name": "cpu",
"version": "2.15",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/cpu_v2_15",
"compilerflags": "",
"linkerflags": "",
},
},
},
"microblaze_0_axi_intc": {"version": "4.1",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"intc_v3_14": {"name": "intc",
"version": "3.14",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/intc_v3_14",
"compilerflags": "",
"linkerflags": "",
},
},
},
"microblaze_0_axi_periph": {"version": "2.1",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"microblaze_0_local_memory_dlmb_bram_if_cntlr": {"version": "4.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"bram_v4_7": {"name": "bram",
"version": "4.7",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/bram_v4_7",
"compilerflags": "",
"linkerflags": "",
},
},
},
"microblaze_0_local_memory_dlmb_v10": {"version": "3.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"microblaze_0_local_memory_ilmb_bram_if_cntlr": {"version": "4.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"bram_v4_7": {"name": "bram",
"version": "4.7",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/bram_v4_7",
"compilerflags": "",
"linkerflags": "",
},
},
},
"microblaze_0_local_memory_ilmb_v10": {"version": "3.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"microblaze_0_local_memory_lmb_bram": {"version": "8.4",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"microblaze_0_xlconcat": {"version": "2.1",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"mig_7series_0": {"version": "4.2",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
"mig_7series_v2_2": {"name": "mig_7series",
"version": "2.2",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/mig_7series_v2_2",
"compilerflags": "",
"linkerflags": "",
},
},
},
"rst_mig_7series_0_100M_1": {"version": "5.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"smartconnect_0": {"version": "1.0",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"util_ds_buf_1": {"version": "2.2",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
"util_ds_buf_2": {"version": "2.2",
"driver_info": {"generic": {"name": "generic",
"version": "3.0 3.1",
"repo": "/opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_0 /opt/Xilinx/Vitis/2022.1/data/embeddedsw/XilinxProcessorIPLib/drivers/generic_v3_1",
},
},
},
}]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.835
!MESSAGE XSCT Command: [::hsi::utils::get_libs_from_sw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/microblaze_0/standalone_microblaze_0/bsp/system.mss], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.836
!MESSAGE XSCT command with result: [::hsi::utils::get_libs_from_sw /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/microblaze_0/standalone_microblaze_0/bsp/system.mss], Result: [null, ]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.836
!MESSAGE XSCT Command: [::hsi::utils::get_sw_libs -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/microblaze_0/standalone_microblaze_0/bsp/system.mss], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.837
!MESSAGE XSCT command with result: [::hsi::utils::get_sw_libs -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/microblaze_0/standalone_microblaze_0/bsp/system.mss], Result: [null, {}]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.846
!MESSAGE XSCT Command: [bsp reload], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:50.852
!MESSAGE XSCT command with result: [bsp reload], Result: [null, ]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:53.349
!MESSAGE XSCT Command: [::hsi::utils::get_all_periphs -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:53.356
!MESSAGE XSCT command with result: [::hsi::utils::get_all_periphs -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa], Result: [null, {"axi_timer_0": {"hier_name": "axi_timer_0",
"type": "axi_timer",
"version": "2.0",
"ip_type": "PERIPHERAL",
},
"axi_uartlite_0": {"hier_name": "axi_uartlite_0",
"type": "axi_uartlite",
"version": "2.0",
"ip_type": "PERIPHERAL",
},
"clk_wiz_0": {"hier_name": "clk_wiz_0",
"type": "clk_wiz",
"version": "6.0",
"ip_type": "PERIPHERAL",
},
"mdm_1": {"hier_name": "mdm_1",
"type": "mdm",
"version": "3.2",
"ip_type": "DEBUG",
},
"microblaze_0": {"hier_name": "microblaze_0",
"type": "microblaze",
"version": "11.0",
"ip_type": "PROCESSOR",
},
"microblaze_0_axi_intc": {"hier_name": "microblaze_0_axi_intc",
"type": "axi_intc",
"version": "4.1",
"ip_type": "INTERRUPT_CNTLR",
},
"microblaze_0_axi_periph": {"hier_name": "microblaze_0_axi_periph",
"type": "axi_interconnect",
"version": "2.1",
"ip_type": "BUS",
},
"microblaze_0_local_memory_dlmb_bram_if_cntlr": {"hier_name": "microblaze_0_local_memory_dlmb_bram_if_cntlr",
"type": "lmb_bram_if_cntlr",
"version": "4.0",
"ip_type": "MEMORY_CNTLR",
},
"microblaze_0_local_memory_dlmb_v10": {"hier_name": "microblaze_0_local_memory_dlmb_v10",
"type": "lmb_v10",
"version": "3.0",
"ip_type": "BUS",
},
"microblaze_0_local_memory_ilmb_bram_if_cntlr": {"hier_name": "microblaze_0_local_memory_ilmb_bram_if_cntlr",
"type": "lmb_bram_if_cntlr",
"version": "4.0",
"ip_type": "MEMORY_CNTLR",
},
"microblaze_0_local_memory_ilmb_v10": {"hier_name": "microblaze_0_local_memory_ilmb_v10",
"type": "lmb_v10",
"version": "3.0",
"ip_type": "BUS",
},
"microblaze_0_local_memory_lmb_bram": {"hier_name": "microblaze_0_local_memory_lmb_bram",
"type": "blk_mem_gen",
"version": "8.4",
"ip_type": "MEMORY",
},
"microblaze_0_xlconcat": {"hier_name": "microblaze_0_xlconcat",
"type": "xlconcat",
"version": "2.1",
"ip_type": "PERIPHERAL",
},
"mig_7series_0": {"hier_name": "mig_7series_0",
"type": "mig_7series",
"version": "4.2",
"ip_type": "MEMORY_CNTLR",
},
"rst_mig_7series_0_100M_1": {"hier_name": "rst_mig_7series_0_100M_1",
"type": "proc_sys_reset",
"version": "5.0",
"ip_type": "PERIPHERAL",
},
"smartconnect_0": {"hier_name": "smartconnect_0",
"type": "smartconnect",
"version": "1.0",
"ip_type": "BUS",
},
"util_ds_buf_1": {"hier_name": "util_ds_buf_1",
"type": "util_ds_buf",
"version": "2.2",
"ip_type": "PERIPHERAL",
},
"util_ds_buf_2": {"hier_name": "util_ds_buf_2",
"type": "util_ds_buf",
"version": "2.2",
"ip_type": "PERIPHERAL",
},
}]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:53.356
!MESSAGE XSCT Command: [::hsi::utils::get_all_register_data -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:53.376
!MESSAGE XSCT command with result: [::hsi::utils::get_all_register_data -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0], Result: [null, {"axi_timer_0": {"TCSR0": {"description": "Timer 0 Control and Status Register",
"address_offset": "0x0",
"access": "read-write",
"size": "32",
"interface": "S_AXI",
"fields": {"MDT0": {"access": "read-write",
"bit_offset": "0",
"bit_range": "",
"bit_width": "1",
"desc": "Timer 0 Mode
0 - Timer mode is generate
1 - Timer mode is capture
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"UDT0": {"access": "read-write",
"bit_offset": "1",
"bit_range": "",
"bit_width": "1",
"desc": "Up/Down Count Timer 0
  0 - Timer functions as up counter
  1 - Timer functions as down counter
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"GENT0": {"access": "read-write",
"bit_offset": "2",
"bit_range": "",
"bit_width": "1",
"desc": "Enable External Generate Signal Timer 0
  0 - Disables external generate signal
  1 - Enables external generate signal
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"CAPT0": {"access": "read-write",
"bit_offset": "3",
"bit_range": "",
"bit_width": "1",
"desc": "Enable External Capture Trigger Timer 0
  0 - Disables external capture trigger
  1 - Enables external capture trigger
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"ARHT0": {"access": "read-write",
"bit_offset": "4",
"bit_range": "",
"bit_width": "1",
"desc": "Auto Reload/Hold Timer 0.
When the timer is in Generate mode, this bit determines whether the counter reloads the generate value and continues running or holds at the termination value. 
In Capture mode, this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held.      0 = Hold counter or capture value. The TLR must be read before providing the external capture.      1 = Reload generate value or overwrite capture value
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"LOAD0": {"access": "read-write",
"bit_offset": "5",
"bit_range": "",
"bit_width": "1",
"desc": "Load Timer 0      0 = No load      1 = Loads timer with value in TLR0 Setting this bit loads timer/counter register (TCR0) with a specified value in the timer/counter load register (TLR0).  This bit prevents the running of the timer/counter; hence, this should be cleared alongside setting Enable Timer/ Counter (ENT0) bit in TCSR0.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"ENIT0": {"access": "read-write",
"bit_offset": "6",
"bit_range": "",
"bit_width": "1",
"desc": "Enable Interrupt for Timer 0
Enables the assertion of the interrupt signal for this timer. Has no effect on the interrupt flag (T0INT) in TCSR0.      0 - Disable interrupt signal   1 - Enable interrupt signal
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"ENT0": {"access": "read-write",
"bit_offset": "7",
"bit_range": "",
"bit_width": "1",
"desc": "Enable Timer 0
  0 - Disable timer (counter halts)
  1 - Enable timer (counter runs)
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"T0INT": {"access": "read-write",
"bit_offset": "8",
"bit_range": "",
"bit_width": "1",
"desc": "Timer 0 Interrupt
Indicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1.
Read:      0 - No interrupt has occurred      1 - Interrupt has occurred  Write:      0 - No change in state of T0INT   1 - Clear T0INT (clear to 0)
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"PWMA0": {"access": "read-write",
"bit_offset": "9",
"bit_range": "",
"bit_width": "1",
"desc": "Enable Pulse Width Modulation for Timer 0      0 - Disable pulse width modulation      1 - Enable pulse width modulation PWM requires using Timer 0 and Timer 1 together as a pair.  Timer 0 sets the period of the PWM output, and Timer 1 sets the high time for the PWM output. For PWM mode, MDT0 and MDT1 must be 0 and C_GEN0_ASSERT and C_GEN1_ASSERT must be 1.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"ENALL": {"access": "read-write",
"bit_offset": "10",
"bit_range": "",
"bit_width": "1",
"desc": "Enable All Timers      0 - No effect on timers      1 - Enable all timers (counters run) This bit is mirrored in all control/status registers and is used to enable all counters simultaneously. Writing a 1 to this bit sets ENALL, ENT0, and ENT1. 
Writing a 0 to this register clears ENALL but has no effect on ENT0 and ENT1. 
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"CASC": {"access": "read-write",
"bit_offset": "11",
"bit_range": "",
"bit_width": "1",
"desc": "Enable cascade mode of timers      0 - Disable cascaded operation      1 - Enable cascaded operation Cascaded operation requires using Timer 0 and Timer 1 together as a pair.  The counting event for the Timer 1 is when the Timer 0 rolls over from all 1s to all 0s or vice-versa when counting down.
TLR0 and TLR1 are used for lower 32-bit and higher 32-bit respectively. Similarly, TCR0 contains lower 32-bits for the 64-bit counter and TCR1 contains the higher 32-bits.
Only TCSR0 is valid for both the timer/counters in this mode.
This CASC bit must be set before enabling the timer/counter.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1103101952,
},
"TLR0": {"description": "Timer 0 Load Register",
"address_offset": "0x4",
"access": "read-write",
"size": "32",
"interface": "S_AXI",
"fields": {"TCLR0": {"access": "read-write",
"bit_offset": "0",
"bit_range": "",
"bit_width": "32",
"desc": "Timer/Counter Load Register
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1103101956,
},
"TCR0": {"description": "Timer 0 Counter Register",
"address_offset": "0x8",
"access": "read-only",
"size": "32",
"interface": "S_AXI",
"fields": {"TCR0": {"access": "read-only",
"bit_offset": "0",
"bit_range": "",
"bit_width": "32",
"desc": "Timer/Counter Register
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1103101960,
},
"TCSR1": {"description": "Timer 1 Control and Status Register",
"address_offset": "0x10",
"access": "read-write",
"size": "32",
"interface": "S_AXI",
"fields": {"MDT1": {"access": "read-write",
"bit_offset": "0",
"bit_range": "",
"bit_width": "1",
"desc": "Timer 1 Mode
  0 - Timer mode is generate
  1 - Timer mode is capture
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"UDT1": {"access": "read-write",
"bit_offset": "1",
"bit_range": "",
"bit_width": "1",
"desc": "Up/Down Count Timer 1
  0 - Timer functions as up counter
  1 - Timer functions as down counter
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"GENT1": {"access": "read-write",
"bit_offset": "2",
"bit_range": "",
"bit_width": "1",
"desc": "Enable External Generate Signal Timer 1
  0 - Disables external generate signal
  1 - Enables external generate signal
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"CAPT1": {"access": "read-write",
"bit_offset": "3",
"bit_range": "",
"bit_width": "1",
"desc": "Enable External Capture Trigger Timer 1
  0 - Disables external capture trigger
  1 - Enables external capture trigger
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"ARHT1": {"access": "read-write",
"bit_offset": "4",
"bit_range": "",
"bit_width": "1",
"desc": "Auto Reload/Hold Timer 1.
When the timer is in Generate mode, this bit determines whether the counter reloads the generate value and continues running or holds at the termination value. 
In Capture mode, this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held.
0 = Hold counter or capture value. The TLR must be read before providing the external capture.   
1 = Reload generate value or overwrite capture value
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"LOAD1": {"access": "read-write",
"bit_offset": "5",
"bit_range": "",
"bit_width": "1",
"desc": "Load Timer 1      0 = No load      1 = Loads timer with value in TLR1 Setting this bit loads timer/counter register (TCR1) with a specified value in the timer/counter load register (TLR1).  This bit prevents the running of the timer/counter; hence, this should be cleared alongside setting Enable Timer/ Counter (ENT1) bit in TCSR1.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"ENIT1": {"access": "read-write",
"bit_offset": "6",
"bit_range": "",
"bit_width": "1",
"desc": "Enable Interrupt for Timer 1
Enables the assertion of the interrupt signal for this timer. Has no effect on the interrupt flag (T1INT) in TCSR1.      0 - Disable interrupt signal      1 - Enable interrupt signal
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"ENT1": {"access": "read-write",
"bit_offset": "7",
"bit_range": "",
"bit_width": "1",
"desc": "Enable Timer 1
  0 - Disable timer (counter halts)
  1 - Enable timer (counter runs)
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"T1INT": {"access": "read-write",
"bit_offset": "8",
"bit_range": "",
"bit_width": "1",
"desc": "Timer 1 Interrupt
Indicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1.
Read:      0 - No interrupt has occurred      1 - Interrupt has occurred  Write:      0 - No change in state of T0INT      1 - Clear T1INT (clear to 0)
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"PWMA1": {"access": "read-write",
"bit_offset": "9",
"bit_range": "",
"bit_width": "1",
"desc": "Enable Pulse Width Modulation for Timer 1      0 - Disable pulse width modulation      1 - Enable pulse width modulation  PWM requires using Timer 0 and Timer 1 together as a pair. Timer 0 sets the period of the PWM output, and Timer 1 sets the high time for the PWM output. For PWM mode, MDT0 and MDT1 must be 0.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"ENALL": {"access": "read-write",
"bit_offset": "10",
"bit_range": "",
"bit_width": "1",
"desc": "Enable All Timers      0 - No effect on timers      1 - Enable all timers (counters run)  This bit is mirrored in all control/status registers and is used to enable all counters simultaneously. Writing a 1 to this bit sets ENALL, ENT0, and ENT1. Writing a 0 to this register clears ENALL but has no effect on ENT0 and ENT1. 
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1103101968,
},
"TLR1": {"description": "Timer 1 Load Register",
"address_offset": "0x14",
"access": "read-write",
"size": "32",
"interface": "S_AXI",
"fields": {"TCLR1": {"access": "read-write",
"bit_offset": "0",
"bit_range": "",
"bit_width": "32",
"desc": "Timer/Counter Load Register
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1103101972,
},
"TCR1": {"description": "Timer 1 Counter Register",
"address_offset": "0x18",
"access": "read-only",
"size": "32",
"interface": "S_AXI",
"fields": {"TCR1": {"access": "read-only",
"bit_offset": "0",
"bit_range": "",
"bit_width": "32",
"desc": "Timer/Counter Register
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1103101976,
},
},
"axi_uartlite_0": {"RX_FIFO": {"description": "Receive data FIFO",
"address_offset": "0x0",
"access": "read-only",
"size": "32",
"interface": "S_AXI",
"fields": {"RX_DATA": {"access": "read-only",
"bit_offset": "0",
"bit_range": "",
"bit_width": "8",
"desc": "UART Receive Data
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1080033280,
},
"TX_FIFO": {"description": "Transmit data FIFO",
"address_offset": "0x4",
"access": "write-only",
"size": "32",
"interface": "S_AXI",
"fields": {"TX_DATA": {"access": "write-only",
"bit_offset": "0",
"bit_range": "",
"bit_width": "8",
"desc": "UART Transmit Data
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1080033284,
},
"CTRL_REG": {"description": "UART Lite control register",
"address_offset": "0xC",
"access": "write-only",
"size": "32",
"interface": "S_AXI",
"fields": {"RST_TXFIFO": {"access": "write-only",
"bit_offset": "0",
"bit_range": "",
"bit_width": "1",
"desc": "Reset/clear the transmit FIFO
Writing a 1 to this bit position clears the transmit FIFO
  0 - Do nothing
  1 - Clear the transmit FIFO
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"RST_RXFIFO": {"access": "write-only",
"bit_offset": "1",
"bit_range": "",
"bit_width": "1",
"desc": "Reset/clear the receive FIFO
Writing a 1 to this bit position clears the receive FIFO
  0 - Do nothing
  1 - Clear the receive FIFO
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"Enable_Intr": {"access": "write-only",
"bit_offset": "4",
"bit_range": "",
"bit_width": "1",
"desc": "Enable interrupt for the AXI UART Lite
  0 - Disable interrupt signal
  1 - Enable interrupt signal
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1080033292,
},
"STAT_REG": {"description": "UART Lite status register",
"address_offset": "0x8",
"access": "read-only",
"size": "32",
"interface": "S_AXI",
"fields": {"RX_FIFO_Valid_Data": {"access": "read-only",
"bit_offset": "0",
"bit_range": "",
"bit_width": "1",
"desc": "Indicates if the receive FIFO has data.
  0 - Receive FIFO is empty
  1 - Receive FIFO has data
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"RX_FIFO_Full": {"access": "read-only",
"bit_offset": "1",
"bit_range": "",
"bit_width": "1",
"desc": "Indicates if the receive FIFO is full.
  0 - Receive FIFO is not full
  1 - Receive FIFO is full
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"TX_FIFO_Empty": {"access": "read-only",
"bit_offset": "2",
"bit_range": "",
"bit_width": "1",
"desc": "Indicates if the transmit FIFO is empty.
  0 - Transmit FIFO is not empty
  1 - Transmit FIFO is empty
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"TX_FIFO_Full": {"access": "read-only",
"bit_offset": "3",
"bit_range": "",
"bit_width": "1",
"desc": "Indicates if the transmit FIFO is full.
  0 - Transmit FIFO is not full
  1 - Transmit FIFO is full
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"Intr_Enabled": {"access": "read-only",
"bit_offset": "4",
"bit_range": "",
"bit_width": "1",
"desc": "Indicates that interrupts is enabled.
  0 - Interrupt is disabled
  1 - Interrupt is enabled
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"Overrun_Error": {"access": "read-only",
"bit_offset": "5",
"bit_range": "",
"bit_width": "1",
"desc": "Indicates that a overrun error has occurred after the last time the status register was read. Overrun is when a new character has been received but the receive FIFO is full. The received character is ignored and not written into the receive FIFO. This bit is cleared when the status register is read.      0 - No overrun error has occurred      1 - Overrun error has occurred
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"Frame_Error": {"access": "read-only",
"bit_offset": "6",
"bit_range": "",
"bit_width": "1",
"desc": "Indicates that a frame error has occurred after the last time the status register was read. Frame error is defined as detection of a stop bit with the value 0. The receive character is ignored and not written to the receive FIFO. This bit is cleared when the status register is read.      0 - No frame error has occurred   1 - Frame error has occurred
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"Parity_Error": {"access": "read-only",
"bit_offset": "7",
"bit_range": "",
"bit_width": "1",
"desc": "Indicates that a parity error has occurred after the last time the status register was read. If the UART is configured without any parity handling, this bit is always 0. The received character is written into the receive FIFO. This bit is cleared when the status register is read.      0 - No parity error has occurred      1 - Parity error has occurred
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1080033288,
},
},
"microblaze_0_axi_intc": {"ISR": {"description": "Interrupt Status Register",
"address_offset": "0x0",
"access": "read-write",
"size": "2",
"interface": "S_AXI",
"fields": {"INT": {"access": "read-write",
"bit_offset": "0",
"bit_range": "",
"bit_width": "2",
"desc": "Interrupt Status Register.
For each bit up to number of periperhal interrupts:
  R - Reads active interrupt signal.
  W - No effect after MER HIE bit has been set, otherwise writes active interrupt signal.
For remaining bits defined by number of software interrupts:
  R - Reads software interrupt value.
  W - Writes software interrupt value.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1092616192,
},
"IPR": {"description": "Interrupt Pending Register",
"address_offset": "0x4",
"access": "read-only",
"size": "2",
"interface": "S_AXI",
"fields": {"INT": {"access": "read-only",
"bit_offset": "0",
"bit_range": "",
"bit_width": "2",
"desc": "Interrupt Pending Register.
For each bit:
  R - Reads logical AND of bits in ISR and IER.
  W - No effect.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1092616196,
},
"IER": {"description": "Interrupt Enable Register",
"address_offset": "0x8",
"access": "read-write",
"size": "2",
"interface": "S_AXI",
"fields": {"INT": {"access": "read-write",
"bit_offset": "0",
"bit_range": "",
"bit_width": "2",
"desc": "Interrupt Enable Register.
For each bit:
  R - Reads interrupt enable value.
  W - Writes interrupt enable value.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1092616200,
},
"IAR": {"description": "Interrupt Acknowledge Register",
"address_offset": "0xC",
"access": "write-only",
"size": "2",
"interface": "S_AXI",
"fields": {"INT": {"access": "write-only",
"bit_offset": "0",
"bit_range": "",
"bit_width": "2",
"desc": "Interrupt Acknowledge Register.
For each bit:
  W - Acknowledge interrupt.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1092616204,
},
"SIE": {"description": "Set Interrupt Enables",
"address_offset": "0x10",
"access": "read-write",
"size": "2",
"interface": "S_AXI",
"fields": {"INT": {"access": "read-write",
"bit_offset": "0",
"bit_range": "",
"bit_width": "2",
"desc": "Set Interrupt Enables
For each bit:
  R - Reads active interrupt.
  W - Writing 1 enables the interrupt, writing 0 has no effect.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1092616208,
},
"CIE": {"description": "Clear Interrupt Enables",
"address_offset": "0x14",
"access": "read-write",
"size": "2",
"interface": "S_AXI",
"fields": {"INT": {"access": "read-write",
"bit_offset": "0",
"bit_range": "",
"bit_width": "2",
"desc": "Clear Interrupt Enables
For each bit:
  R - Reads active interrupt.
  W - Writing 1 disables the interrupt, writing 0 has no effect.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1092616212,
},
"IVR": {"description": "Interrupt Vector Register",
"address_offset": "0x18",
"access": "read-only",
"size": "5",
"interface": "S_AXI",
"fields": {"IVN": {"access": "read-only",
"bit_offset": "0",
"bit_range": "",
"bit_width": "5",
"desc": "Interrupt Vector Number.
  R - Reads ordinal of highest priority, enabled, active interrupt.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1092616216,
},
"MER": {"description": "Master Enable Register",
"address_offset": "0x1C",
"access": "read-write",
"size": "2",
"interface": "S_AXI",
"fields": {"ME": {"access": "read-write",
"bit_offset": "0",
"bit_range": "",
"bit_width": "1",
"desc": "Master IRQ Enable.
  0 - All interrupts disabled.
  1 - All interrupts can be enabled.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
"HIE": {"access": "read-write",
"bit_offset": "1",
"bit_range": "",
"bit_width": "1",
"desc": "Hardware Interrupt Enable.
  0 - HW interrupts disabled.
  1 - HW interrupts enabled.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1092616220,
},
"IMR": {"description": "Interrupt Mode Register",
"address_offset": "0x20",
"access": "read-write",
"size": "2",
"interface": "S_AXI",
"fields": {"INT": {"access": "read-write",
"bit_offset": "0",
"bit_range": "",
"bit_width": "2",
"desc": "Interrupt Mode Register.
For each bit:
  R - Reads interrupt mode.
  W - Sets interrupt mode, where 0 is normal mode and 1 is fast mode.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1092616224,
},
"IVAR[0]": {"description": "Interrupt Vector Address Register 0",
"address_offset": "0x100",
"access": "read-write",
"size": "32",
"interface": "S_AXI",
"fields": {"IVA": {"access": "read-write",
"bit_offset": "0",
"bit_range": "",
"bit_width": "32",
"desc": "Interrupt vector address of active interrupt 0 with highest priority.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1092616448,
},
"IVAR[1]": {"description": "Interrupt Vector Address Register 1",
"address_offset": "0x104",
"access": "read-write",
"size": "32",
"interface": "S_AXI",
"fields": {"IVA": {"access": "read-write",
"bit_offset": "0",
"bit_range": "",
"bit_width": "32",
"desc": "Interrupt vector address of active interrupt 1 with highest priority.
",
"enum_values": "",
"lsb": "",
"mod_write_val": "",
"msb": "",
"read_action": "",
},
},
"memoryAddr": 1092616452,
},
},
"microblaze_0_local_memory_dlmb_bram_if_cntlr": {},
"microblaze_0_local_memory_ilmb_bram_if_cntlr": {},
"mig_7series_0": {},
}]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:53.381
!MESSAGE XSCT Command: [::hsi::utils::get_design_properties -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:53.383
!MESSAGE XSCT command with result: [::hsi::utils::get_design_properties -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa], Result: [null, {"device": "7k325t",
"family": "kintex7",
"timestamp": "Thu Apr 20 17:32:43 2023",
"vivado_version": "2022.1",
"part": "xc7k325tffv676-1",
}]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:53.387
!MESSAGE XSCT Command: [::hsi::utils::get_addr_ranges -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:53.390
!MESSAGE XSCT command with result: [::hsi::utils::get_addr_ranges -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa microblaze_0], Result: [null, {"axi_uartlite_0_S_AXI": {"name": "axi_uartlite_0",
"base": "0x40600000",
"high": "0x4060FFFF",
"size": "65536",
"slaveintf": "S_AXI",
"type": "REGISTER",
"flags": "3",
"segment": "",
"acctype": "",
"tz": "",
},
"microblaze_0_axi_intc_s_axi": {"name": "microblaze_0_axi_intc",
"base": "0x41200000",
"high": "0x4120FFFF",
"size": "65536",
"slaveintf": "s_axi",
"type": "REGISTER",
"flags": "3",
"segment": "",
"acctype": "",
"tz": "",
},
"axi_timer_0_S_AXI": {"name": "axi_timer_0",
"base": "0x41C00000",
"high": "0x41C0FFFF",
"size": "65536",
"slaveintf": "S_AXI",
"type": "REGISTER",
"flags": "3",
"segment": "",
"acctype": "",
"tz": "",
},
"microblaze_0_local_memory_dlmb_bram_if_cntlr_SLMB_Mem": {"name": "microblaze_0_local_memory_dlmb_bram_if_cntlr",
"base": "0x00000000",
"high": "0x0001FFFF",
"size": "131072",
"slaveintf": "SLMB",
"type": "MEMORY",
"flags": "7",
"segment": "Mem",
"acctype": "",
"tz": "",
},
"mig_7series_0_S_AXI_memaddr": {"name": "mig_7series_0",
"base": "0x100000000",
"high": "0x1FFFFFFFF",
"size": "4294967296",
"slaveintf": "S_AXI",
"type": "MEMORY",
"flags": "7",
"segment": "memaddr",
"acctype": "",
"tz": "",
},
}]. Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:53.411
!MESSAGE XSCT Command: [::hsi::utils::get_addr_ranges -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa mdm_1], Thread: main

!ENTRY com.xilinx.sdk.utils 0 0 2023-05-17 14:18:53.413
!MESSAGE XSCT command with result: [::hsi::utils::get_addr_ranges -json /home/macro_fae/work/bmti/mb_max/mb_max.vs/design_1_wrapper/hw/design_1_wrapper.xsa mdm_1], Result: [null, {}]. Thread: main
