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                    &quot;memory_map_ref&quot;: &quot;SLMB&quot;,
                    &quot;parameters&quot;: {
                      &quot;ADDR_WIDTH&quot;: [ { &quot;value&quot;: &quot;36&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;DATA_WIDTH&quot;: [ { &quot;value&quot;: &quot;32&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;READ_WRITE_MODE&quot;: [ { &quot;value&quot;: &quot;READ_WRITE&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;PROTOCOL&quot;: [ { &quot;value&quot;: &quot;STANDARD&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ]
                    },
                    &quot;port_maps&quot;: {
                      &quot;ABUS&quot;: [ { &quot;physical_name&quot;: &quot;LMB_ABus&quot; } ],
                      &quot;ADDRSTROBE&quot;: [ { &quot;physical_name&quot;: &quot;LMB_AddrStrobe&quot; } ],
                      &quot;BE&quot;: [ { &quot;physical_name&quot;: &quot;LMB_BE&quot; } ],
                      &quot;CE&quot;: [ { &quot;physical_name&quot;: &quot;Sl_CE&quot; } ],
                      &quot;READDBUS&quot;: [ { &quot;physical_name&quot;: &quot;Sl_DBus&quot; } ],
                      &quot;READSTROBE&quot;: [ { &quot;physical_name&quot;: &quot;LMB_ReadStrobe&quot; } ],
                      &quot;READY&quot;: [ { &quot;physical_name&quot;: &quot;Sl_Ready&quot; } ],
                      &quot;UE&quot;: [ { &quot;physical_name&quot;: &quot;Sl_UE&quot; } ],
                      &quot;WAIT&quot;: [ { &quot;physical_name&quot;: &quot;Sl_Wait&quot; } ],
                      &quot;WRITEDBUS&quot;: [ { &quot;physical_name&quot;: &quot;LMB_WriteDBus&quot; } ],
                      &quot;WRITESTROBE&quot;: [ { &quot;physical_name&quot;: &quot;LMB_WriteStrobe&quot; } ]
                    }
                  },
                  &quot;BRAM_PORT&quot;: {
                    &quot;vlnv&quot;: &quot;xilinx.com:interface:bram:1.0&quot;,
                    &quot;abstraction_type&quot;: &quot;xilinx.com:interface:bram_rtl:1.0&quot;,
                    &quot;mode&quot;: &quot;master&quot;,
                    &quot;parameters&quot;: {
                      &quot;MEM_SIZE&quot;: [ { &quot;value&quot;: &quot;131072&quot;, &quot;value_src&quot;: &quot;propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;MASTER_TYPE&quot;: [ { &quot;value&quot;: &quot;BRAM_CTRL&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;MEM_WIDTH&quot;: [ { &quot;value&quot;: &quot;32&quot;, &quot;value_src&quot;: &quot;propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;MEM_ECC&quot;: [ { &quot;value&quot;: &quot;NONE&quot;, &quot;value_src&quot;: &quot;propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;READ_WRITE_MODE&quot;: [ { &quot;value&quot;: &quot;&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;READ_LATENCY&quot;: [ { &quot;value&quot;: &quot;1&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ]
                    },
                    &quot;port_maps&quot;: {
                      &quot;ADDR&quot;: [ { &quot;physical_name&quot;: &quot;BRAM_Addr_A&quot; } ],
                      &quot;CLK&quot;: [ { &quot;physical_name&quot;: &quot;BRAM_Clk_A&quot; } ],
                      &quot;DIN&quot;: [ { &quot;physical_name&quot;: &quot;BRAM_Dout_A&quot; } ],
                      &quot;DOUT&quot;: [ { &quot;physical_name&quot;: &quot;BRAM_Din_A&quot; } ],
                      &quot;EN&quot;: [ { &quot;physical_name&quot;: &quot;BRAM_EN_A&quot; } ],
                      &quot;RST&quot;: [ { &quot;physical_name&quot;: &quot;BRAM_Rst_A&quot; } ],
                      &quot;WE&quot;: [ { &quot;physical_name&quot;: &quot;BRAM_WEN_A&quot; } ]
                    }
                  },
                  &quot;CLK.LMB_Clk&quot;: {
                    &quot;vlnv&quot;: &quot;xilinx.com:signal:clock:1.0&quot;,
                    &quot;abstraction_type&quot;: &quot;xilinx.com:signal:clock_rtl:1.0&quot;,
                    &quot;mode&quot;: &quot;slave&quot;,
                    &quot;parameters&quot;: {
                      &quot;ASSOCIATED_BUSIF&quot;: [ { &quot;value&quot;: &quot;SLMB:SLMB1:SLMB2:SLMB3&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;ASSOCIATED_RESET&quot;: [ { &quot;value&quot;: &quot;LMB_Rst&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;FREQ_HZ&quot;: [ { &quot;value&quot;: &quot;100000000&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;user&quot;, &quot;format&quot;: &quot;long&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;FREQ_TOLERANCE_HZ&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;PHASE&quot;: [ { &quot;value&quot;: &quot;0.0&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;float&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;CLK_DOMAIN&quot;: [ { &quot;value&quot;: &quot;/clk_wiz_0_clk_out1&quot;, &quot;value_src&quot;: &quot;ip_propagated&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;ASSOCIATED_PORT&quot;: [ { &quot;value&quot;: &quot;&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;INSERT_VIP&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;resolve_type&quot;: &quot;user&quot;, &quot;format&quot;: &quot;long&quot;, &quot;usage&quot;: &quot;simulation.rtl&quot;, &quot;is_static_object&quot;: false } ]
                    },
                    &quot;port_maps&quot;: {
                      &quot;CLK&quot;: [ { &quot;physical_name&quot;: &quot;LMB_Clk&quot; } ]
                    }
                  },
                  &quot;RST.LMB_Rst&quot;: {
                    &quot;vlnv&quot;: &quot;xilinx.com:signal:reset:1.0&quot;,
                    &quot;abstraction_type&quot;: &quot;xilinx.com:signal:reset_rtl:1.0&quot;,
                    &quot;mode&quot;: &quot;slave&quot;,
                    &quot;parameters&quot;: {
                      &quot;POLARITY&quot;: [ { &quot;value&quot;: &quot;ACTIVE_HIGH&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;TYPE&quot;: [ { &quot;value&quot;: &quot;INTERCONNECT&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;value_permission&quot;: &quot;bd&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;INSERT_VIP&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;resolve_type&quot;: &quot;user&quot;, &quot;format&quot;: &quot;long&quot;, &quot;usage&quot;: &quot;simulation.rtl&quot;, &quot;is_static_object&quot;: false } ]
                    },
                    &quot;port_maps&quot;: {
                      &quot;RST&quot;: [ { &quot;physical_name&quot;: &quot;LMB_Rst&quot; } ]
                    }
                  },
                  &quot;CLK.S_AXI_CTRL_ACLK&quot;: {
                    &quot;vlnv&quot;: &quot;xilinx.com:signal:clock:1.0&quot;,
                    &quot;abstraction_type&quot;: &quot;xilinx.com:signal:clock_rtl:1.0&quot;,
                    &quot;mode&quot;: &quot;slave&quot;,
                    &quot;parameters&quot;: {
                      &quot;ASSOCIATED_BUSIF&quot;: [ { &quot;value&quot;: &quot;S_AXI_CTRL&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;ASSOCIATED_RESET&quot;: [ { &quot;value&quot;: &quot;S_AXI_CTRL_ARESETN&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;FREQ_HZ&quot;: [ { &quot;value&quot;: &quot;100000000&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;FREQ_TOLERANCE_HZ&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;long&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;PHASE&quot;: [ { &quot;value&quot;: &quot;0.0&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;format&quot;: &quot;float&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;CLK_DOMAIN&quot;: [ { &quot;value&quot;: &quot;&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;ASSOCIATED_PORT&quot;: [ { &quot;value&quot;: &quot;&quot;, &quot;resolve_type&quot;: &quot;generated&quot;, &quot;is_static_object&quot;: false } ],
                      &quot;INSERT_VIP&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;resolve_type&quot;: &quot;user&quot;, &quot;format&quot;: &quot;long&quot;, &quot;usage&quot;: &quot;simulation.rtl&quot;, &quot;is_static_object&quot;: false } ]
                    }
                  },
                  &quot;RST.S_AXI_CTRL_ARESETN&quot;: {
                    &quot;vlnv&quot;: &quot;xilinx.com:signal:reset:1.0&quot;,
                    &quot;abstraction_type&quot;: &quot;xilinx.com:signal:reset_rtl:1.0&quot;,
                    &quot;mode&quot;: &quot;slave&quot;,
                    &quot;parameters&quot;: {
                      &quot;POLARITY&quot;: [ { &quot;value&quot;: &quot;ACTIVE_LOW&quot;, &quot;value_src&quot;: &quot;constant&quot;, &quot;usage&quot;: &quot;all&quot; } ],
                      &quot;INSERT_VIP&quot;: [ { &quot;value&quot;: &quot;0&quot;, &quot;resolve_type&quot;: &quot;user&quot;, &quot;format&quot;: &quot;long&quot;, &quot;usage&quot;: &quot;simulation.rtl&quot;, &quot;is_static_object&quot;: false } ]
                    }
                  }
                },
                &quot;memory_maps&quot;: {
                  &quot;SLMB&quot;: {
                    &quot;description&quot;: &quot;SLMB memory map&quot;,
                    &quot;address_blocks&quot;: {
                      &quot;Mem&quot;: {
                        &quot;base_address&quot;: &quot;0&quot;,
                        &quot;range&quot;: &quot;8192&quot;,
                        &quot;usage&quot;: &quot;memory&quot;,
                        &quot;access&quot;: &quot;read-write&quot;,
                        &quot;parameters&quot;: {
                          &quot;OFFSET_BASE_PARAM&quot;: [ { &quot;value&quot;: &quot;C_BASEADDR&quot; } ],
                          &quot;OFFSET_HIGH_PARAM&quot;: [ { &quot;value&quot;: &quot;C_HIGHADDR&quot; } ]
                        }
                      }
                    }
                  },
                  &quot;SLMB1&quot;: {
                    &quot;description&quot;: &quot;SLMB1 memory map&quot;,
                    &quot;address_blocks&quot;: {
                      &quot;Mem&quot;: {
                        &quot;base_address&quot;: &quot;0&quot;,
                        &quot;range&quot;: &quot;8192&quot;,
                        &quot;usage&quot;: &quot;memory&quot;,
                        &quot;access&quot;: &quot;read-write&quot;,
                        &quot;parameters&quot;: {
                          &quot;OFFSET_BASE_PARAM&quot;: [ { &quot;value&quot;: &quot;C_BASEADDR&quot; } ],
                          &quot;OFFSET_HIGH_PARAM&quot;: [ { &quot;value&quot;: &quot;C_HIGHADDR&quot; } ]
                        }
                      }
                    }
                  },
                  &quot;SLMB2&quot;: {
                    &quot;description&quot;: &quot;SLMB2 memory map&quot;,
                    &quot;address_blocks&quot;: {
                      &quot;Mem&quot;: {
                        &quot;base_address&quot;: &quot;0&quot;,
                        &quot;range&quot;: &quot;8192&quot;,
                        &quot;usage&quot;: &quot;memory&quot;,
                        &quot;access&quot;: &quot;read-write&quot;,
                        &quot;parameters&quot;: {
                          &quot;OFFSET_BASE_PARAM&quot;: [ { &quot;value&quot;: &quot;C_BASEADDR&quot; } ],
                          &quot;OFFSET_HIGH_PARAM&quot;: [ { &quot;value&quot;: &quot;C_HIGHADDR&quot; } ]
                        }
                      }
                    }
                  },
                  &quot;SLMB3&quot;: {
                    &quot;description&quot;: &quot;SLMB3 memory map&quot;,
                    &quot;address_blocks&quot;: {
                      &quot;Mem&quot;: {
                        &quot;base_address&quot;: &quot;0&quot;,
                        &quot;range&quot;: &quot;8192&quot;,
                        &quot;usage&quot;: &quot;memory&quot;,
                        &quot;access&quot;: &quot;read-write&quot;,
                        &quot;parameters&quot;: {
                          &quot;OFFSET_BASE_PARAM&quot;: [ { &quot;value&quot;: &quot;C_BASEADDR&quot; } ],
                          &quot;OFFSET_HIGH_PARAM&quot;: [ { &quot;value&quot;: &quot;C_HIGHADDR&quot; } ]
                        }
                      }
                    }
                  },
                  &quot;S_AXI_CTRL&quot;: {
                    &quot;description&quot;: &quot;S_AXI_CTRL memory map&quot;,
                    &quot;address_blocks&quot;: {
                      &quot;Reg&quot;: {
                        &quot;base_address&quot;: &quot;0&quot;,
                        &quot;range&quot;: &quot;4096&quot;,
                        &quot;display_name&quot;: &quot;Reg&quot;,
                        &quot;description&quot;: &quot;Register Block&quot;,
                        &quot;usage&quot;: &quot;register&quot;,
                        &quot;access&quot;: &quot;read-write&quot;
                      }
                    }
                  }
                }
              }
            }"/>
          </xilinx:boundaryDescriptionInfo>
        </xilinx:componentInstanceExtensions>
      </spirit:vendorExtensions>
    </spirit:componentInstance>
  </spirit:componentInstances>
</spirit:design>
