{
  "design": {
    "design_info": {
      "boundary_crc": "0x7F044721AADE5F91",
      "design_src": "SBD",
      "device": "xc7k325tffv676-1",
      "name": "bd_48ac",
      "rev_ctrl_bd_flag": "RevCtrlBdOff",
      "scoped": "true",
      "synth_flow_mode": "None",
      "tool_version": "2022.1",
      "validated": "true",
      "gen_directory": "."
    },
    "design_tree": {
      "clk_map": {
        "one": "",
        "psr0": "",
        "psr_aclk": "",
        "psr_aclk1": ""
      },
      "switchboards": {
        "ar_switchboard": "",
        "r_switchboard": "",
        "aw_switchboard": "",
        "w_switchboard": "",
        "b_switchboard": ""
      },
      "s00_entry_pipeline": {
        "s00_mmu": "",
        "s00_transaction_regulator": "",
        "s00_si_converter": ""
      },
      "s00_axi2sc": "",
      "s00_nodes": {
        "s00_ar_node": "",
        "s00_r_node": "",
        "s00_aw_node": "",
        "s00_w_node": "",
        "s00_b_node": ""
      },
      "s01_entry_pipeline": {
        "s01_mmu": "",
        "s01_transaction_regulator": "",
        "s01_si_converter": ""
      },
      "s01_axi2sc": "",
      "s01_nodes": {
        "s01_ar_node": "",
        "s01_r_node": ""
      },
      "m00_sc2axi": "",
      "m00_nodes": {
        "m00_ar_node": "",
        "m00_r_node": "",
        "m00_aw_node": "",
        "m00_w_node": "",
        "m00_b_node": ""
      },
      "m00_exit_pipeline": {
        "m00_exit": ""
      }
    },
    "interface_ports": {
      "S00_AXI": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "36",
            "value_src": "auto_prop"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "auto_prop"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "auto_prop"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "const_prop"
          },
          "CLK_DOMAIN": {
            "value": "/clk_wiz_0_clk_out1",
            "value_src": "ip_prop"
          },
          "DATA_WIDTH": {
            "value": "32",
            "value_src": "auto_prop"
          },
          "FREQ_HZ": {
            "value": "100000000",
            "value_src": "ip_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "auto_prop"
          },
          "HAS_BURST": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_CACHE": {
            "value": "1",
            "value_src": "auto_prop"
          },
          "HAS_LOCK": {
            "value": "1",
            "value_src": "auto_prop"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "auto_prop"
          },
          "HAS_QOS": {
            "value": "1",
            "value_src": "auto_prop"
          },
          "HAS_REGION": {
            "value": "0",
            "value_src": "constant"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "auto_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "auto_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "const_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "4",
            "value_src": "const_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "const_prop"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "32"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "const_prop"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "ip_prop"
          },
          "PROTOCOL": {
            "value": "AXI4",
            "value_src": "const_prop"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "const_prop"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "const_prop"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "const_prop"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "const_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "const_prop"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "const_prop"
          }
        },
        "address_space_ref": "S00_AXI",
        "base_address": {
          "minimum": "0x00000000",
          "maximum": "0x000FFFFFFFFF",
          "width": "36"
        }
      },
      "S01_AXI": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "36",
            "value_src": "auto_prop"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "auto_prop"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "auto_prop"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "const_prop"
          },
          "CLK_DOMAIN": {
            "value": "/clk_wiz_0_clk_out1",
            "value_src": "ip_prop"
          },
          "DATA_WIDTH": {
            "value": "32",
            "value_src": "auto_prop"
          },
          "FREQ_HZ": {
            "value": "100000000",
            "value_src": "ip_prop"
          },
          "HAS_BRESP": {
            "value": "0",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_CACHE": {
            "value": "1",
            "value_src": "auto_prop"
          },
          "HAS_LOCK": {
            "value": "0",
            "value_src": "const_prop"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "auto_prop"
          },
          "HAS_QOS": {
            "value": "1",
            "value_src": "auto_prop"
          },
          "HAS_REGION": {
            "value": "0",
            "value_src": "constant"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "auto_prop"
          },
          "HAS_WSTRB": {
            "value": "0",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "const_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "8",
            "value_src": "const_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "8"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "const_prop"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "ip_prop"
          },
          "PROTOCOL": {
            "value": "AXI4",
            "value_src": "const_prop"
          },
          "READ_WRITE_MODE": {
            "value": "READ_ONLY",
            "value_src": "const_prop"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "const_prop"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "const_prop"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "const_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "const_prop"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "const_prop"
          }
        },
        "address_space_ref": "S01_AXI",
        "base_address": {
          "minimum": "0x00000000",
          "maximum": "0x000FFFFFFFFF",
          "width": "36"
        }
      },
      "M00_AXI": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32",
            "value_src": "default"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_mig_7series_0_0_ui_clk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "64",
            "value_src": "ip"
          },
          "FREQ_HZ": {
            "value": "200000000",
            "value_src": "default_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "default"
          },
          "HAS_BURST": {
            "value": "1",
            "value_src": "default"
          },
          "HAS_CACHE": {
            "value": "1",
            "value_src": "default"
          },
          "HAS_LOCK": {
            "value": "1",
            "value_src": "default"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "default"
          },
          "HAS_QOS": {
            "value": "1",
            "value_src": "default"
          },
          "HAS_REGION": {
            "value": "0",
            "value_src": "constant"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "default"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "default"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "4"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "8"
          },
          "NUM_READ_THREADS": {
            "value": "1"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "32"
          },
          "NUM_WRITE_THREADS": {
            "value": "1"
          },
          "PHASE": {
            "value": "0",
            "value_src": "default_prop"
          },
          "PROTOCOL": {
            "value": "AXI4",
            "value_src": "default"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "M00_AXI"
      }
    },
    "ports": {
      "aclk": {
        "type": "clk",
        "direction": "I",
        "parameters": {
          "ASSOCIATED_BUSIF": {
            "value": "M00_AXI"
          },
          "ASSOCIATED_CLKEN": {
            "value": "m_sc_aclken",
            "value_src": "constant"
          },
          "CLK_DOMAIN": {
            "value": "design_1_mig_7series_0_0_ui_clk",
            "value_src": "default_prop"
          },
          "FREQ_HZ": {
            "value": "200000000",
            "value_src": "default_prop"
          },
          "FREQ_TOLERANCE_HZ": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0",
            "value_src": "default_prop"
          }
        }
      },
      "aclk1": {
        "type": "clk",
        "direction": "I",
        "parameters": {
          "ASSOCIATED_BUSIF": {
            "value": "S00_AXI:S01_AXI"
          },
          "ASSOCIATED_CLKEN": {
            "value": "m_sc_aclken",
            "value_src": "constant"
          },
          "CLK_DOMAIN": {
            "value": "/clk_wiz_0_clk_out1",
            "value_src": "ip_prop"
          },
          "FREQ_HZ": {
            "value": "100000000",
            "value_src": "ip_prop"
          },
          "FREQ_TOLERANCE_HZ": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "ip_prop"
          }
        }
      },
      "aresetn": {
        "type": "rst",
        "direction": "I",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW"
          }
        }
      }
    },
    "components": {
      "clk_map": {
        "ports": {
          "S00_ACLK": {
            "type": "clk",
            "direction": "O"
          },
          "S00_ARESETN": {
            "type": "rst",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "S01_ACLK": {
            "type": "clk",
            "direction": "O"
          },
          "S01_ARESETN": {
            "type": "rst",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "M00_ACLK": {
            "type": "clk",
            "direction": "O"
          },
          "M00_ARESETN": {
            "type": "rst",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "swbd_aclk": {
            "type": "clk",
            "direction": "O"
          },
          "swbd_aresetn": {
            "type": "rst",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "aresetn": {
            "type": "rst",
            "direction": "I"
          },
          "aresetn_out": {
            "type": "rst",
            "direction": "O"
          },
          "aclk": {
            "type": "clk",
            "direction": "I"
          },
          "aclk1": {
            "type": "clk",
            "direction": "I"
          }
        },
        "components": {
          "one": {
            "vlnv": "xilinx.com:ip:xlconstant:1.1",
            "xci_name": "bd_48ac_one_0",
            "xci_path": "ip/ip_0/bd_48ac_one_0.xci",
            "inst_hier_path": "clk_map/one"
          },
          "psr0": {
            "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
            "xci_name": "bd_48ac_psr0_0",
            "xci_path": "ip/ip_1/bd_48ac_psr0_0.xci",
            "inst_hier_path": "clk_map/psr0",
            "parameters": {
              "C_AUX_RESET_HIGH": {
                "value": "0"
              },
              "C_AUX_RST_WIDTH": {
                "value": "1"
              }
            }
          },
          "psr_aclk": {
            "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
            "xci_name": "bd_48ac_psr_aclk_0",
            "xci_path": "ip/ip_2/bd_48ac_psr_aclk_0.xci",
            "inst_hier_path": "clk_map/psr_aclk",
            "parameters": {
              "C_AUX_RESET_HIGH": {
                "value": "0"
              },
              "C_AUX_RST_WIDTH": {
                "value": "1"
              }
            }
          },
          "psr_aclk1": {
            "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
            "xci_name": "bd_48ac_psr_aclk1_0",
            "xci_path": "ip/ip_3/bd_48ac_psr_aclk1_0.xci",
            "inst_hier_path": "clk_map/psr_aclk1",
            "parameters": {
              "C_AUX_RESET_HIGH": {
                "value": "0"
              },
              "C_AUX_RST_WIDTH": {
                "value": "1"
              }
            }
          }
        },
        "nets": {
          "clk_map_aclk1_net": {
            "ports": [
              "aclk1",
              "S00_ACLK",
              "S01_ACLK",
              "psr0/slowest_sync_clk",
              "psr_aclk1/slowest_sync_clk"
            ]
          },
          "clk_map_aclk_net": {
            "ports": [
              "aclk",
              "M00_ACLK",
              "swbd_aclk",
              "psr_aclk/slowest_sync_clk"
            ]
          },
          "clk_map_aresetn_net": {
            "ports": [
              "aresetn",
              "psr0/aux_reset_in",
              "psr_aclk/aux_reset_in",
              "psr_aclk1/aux_reset_in"
            ]
          },
          "one_dout": {
            "ports": [
              "one/dout",
              "psr0/ext_reset_in"
            ]
          },
          "psr0_interconnect_aresetn": {
            "ports": [
              "psr0/interconnect_aresetn",
              "psr_aclk/ext_reset_in",
              "psr_aclk1/ext_reset_in"
            ]
          },
          "psr_aclk1_interconnect_aresetn": {
            "ports": [
              "psr_aclk1/interconnect_aresetn",
              "S00_ARESETN",
              "S01_ARESETN"
            ]
          },
          "psr_aclk_interconnect_aresetn": {
            "ports": [
              "psr_aclk/interconnect_aresetn",
              "M00_ARESETN",
              "swbd_aresetn"
            ]
          }
        }
      },
      "switchboards": {
        "interface_ports": {
          "S00_SC_AR": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "S01_SC_AR": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "M00_SC_AR": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "S00_SC_R": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "M00_SC_R": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "M01_SC_R": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "S00_SC_AW": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "S01_SC_AW": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "M00_SC_AW": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "S00_SC_W": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "S01_SC_W": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "M00_SC_W": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "S00_SC_B": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "M00_SC_B": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          },
          "M01_SC_B": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          }
        },
        "ports": {
          "aclk": {
            "type": "clk",
            "direction": "I"
          },
          "aresetn": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "ar_switchboard": {
            "vlnv": "xilinx.com:ip:sc_switchboard:1.0",
            "xci_name": "bd_48ac_arsw_0",
            "xci_path": "ip/ip_4/bd_48ac_arsw_0.xci",
            "inst_hier_path": "switchboards/ar_switchboard",
            "parameters": {
              "M00_S00_CONNECTIVITY": {
                "value": "1"
              },
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                  "M01_SC"
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                "value": "1"
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                "value": "1"
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                "vlnv": "xilinx.com:interface:sc_rtl:1.0",
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                  "M00_SC"
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                "vlnv": "xilinx.com:interface:sc_rtl:1.0",
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                  "M00_SC"
                ]
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                "value": "1"
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                "value": "7"
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                "value": "0"
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                "value": "0"
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                  "M00_SC",
                  "M01_SC"
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              "S00_SC_W",
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              "w_switchboard/M00_SC"
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              "SEG000_SEP_ROUTE": {
                "value": "0b0000000000000000000000000000000000000000000000000000000000000000"
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              "S_AWUSER_WIDTH": {
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              "S_BUSER_WIDTH": {
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              "S_PROTOCOL": {
                "value": "AXI4"
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                "bridges": [
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                "value": "36"
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              },
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              },
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                "value": "32"
              },
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                "value": "READ_WRITE"
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                "value": "AXI4"
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              },
              "SEP000_WDATA_WIDTH": {
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              "S_WUSER_BITS_PER_BYTE": {
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                "bridges": [
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          "SC_WUSER_BITS_PER_BYTE": {
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            "bridges": [
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              "M_SC_AW"
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            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
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            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
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            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
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            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
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            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
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            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
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            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
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            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
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            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
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            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:sc:1.0",
            "vlnv": "xilinx.com:interface:sc_rtl:1.0"
          }
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            "type": "clk",
            "direction": "I"
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          "s_sc_resetn": {
            "type": "rst",
            "direction": "I"
          },
          "m_sc_clk": {
            "type": "clk",
            "direction": "I"
          },
          "m_sc_resetn": {
            "type": "rst",
            "direction": "I"
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        "components": {
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            "vlnv": "xilinx.com:ip:sc_node:1.0",
            "xci_name": "bd_48ac_sarn_0",
            "xci_path": "ip/ip_13/bd_48ac_sarn_0.xci",
            "inst_hier_path": "s00_nodes/s00_ar_node",
            "parameters": {
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                "value": "0"
              },
              "ACLK_RELATIONSHIP": {
                "value": "0"
              },
              "ADDR_WIDTH": {
                "value": "36"
              },
              "CHANNEL": {
                "value": "2"
              },
              "ID_WIDTH": {
                "value": "2"
              },
              "M00_NUM_BYTES": {
                "value": "8"
              },
              "M01_NUM_BYTES": {
                "value": "8"
              },
              "M02_NUM_BYTES": {
                "value": "8"
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              "M03_NUM_BYTES": {
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              "M04_NUM_BYTES": {
                "value": "8"
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              "M05_NUM_BYTES": {
                "value": "8"
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              "M06_NUM_BYTES": {
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              "M07_NUM_BYTES": {
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              },
              "M08_NUM_BYTES": {
                "value": "8"
              },
              "M09_NUM_BYTES": {
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          },
          "m_axi_aresetn": {
            "type": "rst",
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            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
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        "ports": {
          "aclk": {
            "type": "clk",
            "direction": "I"
          },
          "aresetn": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "m00_exit": {
            "vlnv": "xilinx.com:ip:sc_exit:1.0",
            "xci_name": "bd_48ac_m00e_0",
            "xci_path": "ip/ip_30/bd_48ac_m00e_0.xci",
            "inst_hier_path": "m00_exit_pipeline/m00_exit",
            "parameters": {
              "ADDR_WIDTH": {
                "value": "32"
              },
              "HAS_BURST": {
                "value": "1"
              },
              "HAS_LOCK": {
                "value": "0"
              },
              "IS_CASCADED": {
                "value": "0"
              },
              "MAX_RUSER_BITS_PER_BYTE": {
                "value": "0"
              },
              "MAX_WUSER_BITS_PER_BYTE": {
                "value": "0"
              },
              "MEP_IDENTIFIER_WIDTH": {
                "value": "2"
              },
              "M_ARUSER_WIDTH": {
                "value": "0"
              },
              "M_AWUSER_WIDTH": {
                "value": "0"
              },
              "M_BUSER_WIDTH": {
                "value": "0"
              },
              "M_ID_WIDTH": {
                "value": "0"
              },
              "M_MAX_BURST_LENGTH": {
                "value": "4"
              },
              "M_PROTOCOL": {
                "value": "AXI4"
              },
              "M_RUSER_BITS_PER_BYTE": {
                "value": "0"
              },
              "M_RUSER_WIDTH": {
                "value": "0"
              },
              "M_WUSER_BITS_PER_BYTE": {
                "value": "0"
              },
              "M_WUSER_WIDTH": {
                "value": "0"
              },
              "NUM_MSC": {
                "value": "1"
              },
              "NUM_READ_OUTSTANDING": {
                "value": "8"
              },
              "NUM_WRITE_OUTSTANDING": {
                "value": "32"
              },
              "RDATA_WIDTH": {
                "value": "64"
              },
              "READ_WRITE_MODE": {
                "value": "READ_WRITE"
              },
              "SSC000_ROUTE": {
                "value": "0b00"
              },
              "SSC001_ROUTE": {
                "value": "0b01"
              },
              "SSC002_ROUTE": {
                "value": "0b10"
              },
              "SSC003_ROUTE": {
                "value": "0b00"
              },
              "SSC_ROUTE_WIDTH": {
                "value": "2"
              },
              "S_ID_WIDTH": {
                "value": "2"
              },
              "WDATA_WIDTH": {
                "value": "64"
              }
            },
            "interface_ports": {
              "S_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M_AXI"
                ]
              }
            }
          }
        },
        "interface_nets": {
          "m00_exit_M_AXI": {
            "interface_ports": [
              "m_axi",
              "m00_exit/M_AXI"
            ]
          },
          "s_axi_1": {
            "interface_ports": [
              "s_axi",
              "m00_exit/S_AXI"
            ]
          }
        },
        "nets": {
          "aclk_1": {
            "ports": [
              "aclk",
              "m00_exit/aclk"
            ]
          },
          "aresetn_1": {
            "ports": [
              "aresetn",
              "m00_exit/aresetn"
            ]
          }
        }
      }
    },
    "interface_nets": {
      "S00_AXI_1": {
        "interface_ports": [
          "S00_AXI",
          "s00_entry_pipeline/s_axi"
        ]
      },
      "S01_AXI_1": {
        "interface_ports": [
          "S01_AXI",
          "s01_entry_pipeline/s_axi"
        ]
      },
      "S_SC_AR_1": {
        "interface_ports": [
          "s00_nodes/S_SC_AR",
          "s00_axi2sc/M_SC_AR"
        ]
      },
      "S_SC_AR_2": {
        "interface_ports": [
          "s01_nodes/S_SC_AR",
          "s01_axi2sc/M_SC_AR"
        ]
      },
      "S_SC_AR_3": {
        "interface_ports": [
          "m00_nodes/S_SC_AR",
          "switchboards/M00_SC_AR"
        ]
      },
      "S_SC_AW_1": {
        "interface_ports": [
          "s00_nodes/S_SC_AW",
          "s00_axi2sc/M_SC_AW"
        ]
      },
      "S_SC_AW_2": {
        "interface_ports": [
          "m00_nodes/S_SC_AW",
          "switchboards/M00_SC_AW"
        ]
      },
      "S_SC_B_1": {
        "interface_ports": [
          "s00_nodes/S_SC_B",
          "switchboards/M00_SC_B"
        ]
      },
      "S_SC_B_2": {
        "interface_ports": [
          "m00_nodes/S_SC_B",
          "m00_sc2axi/M_SC_B"
        ]
      },
      "S_SC_R_1": {
        "interface_ports": [
          "s00_nodes/S_SC_R",
          "switchboards/M00_SC_R"
        ]
      },
      "S_SC_R_2": {
        "interface_ports": [
          "s01_nodes/S_SC_R",
          "switchboards/M01_SC_R"
        ]
      },
      "S_SC_R_3": {
        "interface_ports": [
          "m00_nodes/S_SC_R",
          "m00_sc2axi/M_SC_R"
        ]
      },
      "S_SC_W_1": {
        "interface_ports": [
          "s00_nodes/S_SC_W",
          "s00_axi2sc/M_SC_W"
        ]
      },
      "S_SC_W_2": {
        "interface_ports": [
          "m00_nodes/S_SC_W",
          "switchboards/M00_SC_W"
        ]
      },
      "m00_exit_pipeline_m_axi": {
        "interface_ports": [
          "M00_AXI",
          "m00_exit_pipeline/m_axi"
        ]
      },
      "m00_nodes_M_SC_AR": {
        "interface_ports": [
          "m00_nodes/M_SC_AR",
          "m00_sc2axi/S_SC_AR"
        ]
      },
      "m00_nodes_M_SC_AW": {
        "interface_ports": [
          "m00_nodes/M_SC_AW",
          "m00_sc2axi/S_SC_AW"
        ]
      },
      "m00_nodes_M_SC_B": {
        "interface_ports": [
          "m00_nodes/M_SC_B",
          "switchboards/S00_SC_B"
        ]
      },
      "m00_nodes_M_SC_R": {
        "interface_ports": [
          "m00_nodes/M_SC_R",
          "switchboards/S00_SC_R"
        ]
      },
      "m00_nodes_M_SC_W": {
        "interface_ports": [
          "m00_nodes/M_SC_W",
          "m00_sc2axi/S_SC_W"
        ]
      },
      "m00_sc2axi_M_AXI": {
        "interface_ports": [
          "m00_sc2axi/M_AXI",
          "m00_exit_pipeline/s_axi"
        ]
      },
      "s00_entry_pipeline_m_axi": {
        "interface_ports": [
          "s00_entry_pipeline/m_axi",
          "s00_axi2sc/S_AXI"
        ]
      },
      "s00_nodes_M_SC_AR": {
        "interface_ports": [
          "s00_nodes/M_SC_AR",
          "switchboards/S00_SC_AR"
        ]
      },
      "s00_nodes_M_SC_AW": {
        "interface_ports": [
          "s00_nodes/M_SC_AW",
          "switchboards/S00_SC_AW"
        ]
      },
      "s00_nodes_M_SC_B": {
        "interface_ports": [
          "s00_nodes/M_SC_B",
          "s00_axi2sc/S_SC_B"
        ]
      },
      "s00_nodes_M_SC_R": {
        "interface_ports": [
          "s00_nodes/M_SC_R",
          "s00_axi2sc/S_SC_R"
        ]
      },
      "s00_nodes_M_SC_W": {
        "interface_ports": [
          "s00_nodes/M_SC_W",
          "switchboards/S00_SC_W"
        ]
      },
      "s01_entry_pipeline_m_axi": {
        "interface_ports": [
          "s01_entry_pipeline/m_axi",
          "s01_axi2sc/S_AXI"
        ]
      },
      "s01_nodes_M_SC_AR": {
        "interface_ports": [
          "s01_nodes/M_SC_AR",
          "switchboards/S01_SC_AR"
        ]
      },
      "s01_nodes_M_SC_R": {
        "interface_ports": [
          "s01_nodes/M_SC_R",
          "s01_axi2sc/S_SC_R"
        ]
      }
    },
    "nets": {
      "aclk1_1": {
        "ports": [
          "aclk1",
          "clk_map/aclk1"
        ]
      },
      "aclk_1": {
        "ports": [
          "clk_map/S00_ACLK",
          "s00_entry_pipeline/aclk",
          "s00_axi2sc/aclk",
          "s00_nodes/s_sc_clk"
        ]
      },
      "aclk_2": {
        "ports": [
          "clk_map/S01_ACLK",
          "s01_entry_pipeline/aclk",
          "s01_axi2sc/aclk",
          "s01_nodes/s_sc_clk"
        ]
      },
      "aclk_net": {
        "ports": [
          "aclk",
          "clk_map/aclk"
        ]
      },
      "aresetn_1": {
        "ports": [
          "aresetn",
          "clk_map/aresetn"
        ]
      },
      "aresetn_2": {
        "ports": [
          "clk_map/S00_ARESETN",
          "s00_entry_pipeline/aresetn",
          "s00_nodes/s_sc_resetn"
        ]
      },
      "aresetn_3": {
        "ports": [
          "clk_map/S01_ARESETN",
          "s01_entry_pipeline/aresetn",
          "s01_nodes/s_sc_resetn"
        ]
      },
      "aresetn_net": {
        "ports": [
          "clk_map/aresetn_out"
        ]
      },
      "clk_map_M00_ACLK": {
        "ports": [
          "clk_map/M00_ACLK",
          "m00_sc2axi/aclk",
          "m00_nodes/m_axi_aclk",
          "m00_exit_pipeline/aclk"
        ]
      },
      "m_axi_aresetn_1": {
        "ports": [
          "clk_map/M00_ARESETN",
          "m00_nodes/m_axi_aresetn",
          "m00_exit_pipeline/aresetn"
        ]
      },
      "swbd_aclk_net": {
        "ports": [
          "clk_map/swbd_aclk",
          "switchboards/aclk",
          "s00_nodes/m_sc_clk",
          "s01_nodes/m_sc_clk",
          "m00_nodes/s_axi_aclk"
        ]
      },
      "swbd_aresetn_net": {
        "ports": [
          "clk_map/swbd_aresetn",
          "switchboards/aresetn",
          "s00_nodes/m_sc_resetn",
          "s01_nodes/m_sc_resetn",
          "m00_nodes/s_axi_aresetn"
        ]
      }
    },
    "addressing": {
      "/": {
        "address_spaces": {
          "S00_AXI": {
            "range": "64G",
            "width": "36"
          },
          "S01_AXI": {
            "range": "64G",
            "width": "36"
          }
        },
        "memory_maps": {
          "M00_AXI": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          }
        }
      }
    }
  }
}