NUM_SI 2
NUM_MI 1
NUM_CLKS 2
S00_AXI.CONFIG.ID_WIDTH 0
S00_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
S00_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
S00_AXI.CONFIG.HAS_BURST 1
S00_AXI.CONFIG.HAS_LOCK 1
S00_AXI.CONFIG.ADDR_WIDTH 36
S00_AXI.CONFIG.PROTOCOL AXI4
S00_AXI.CONFIG.AWUSER_WIDTH 0
S00_AXI.CONFIG.ARUSER_WIDTH 0
S00_AXI.CONFIG.WUSER_WIDTH 0
S00_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
S00_AXI.CONFIG.RUSER_WIDTH 0
S00_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
S00_AXI.CONFIG.BUSER_WIDTH 0
S00_AXI.CONFIG.NUM_READ_OUTSTANDING 2
S00_AXI.CONFIG.NUM_WRITE_OUTSTANDING 32
S00_AXI.CONFIG.NUM_READ_THREADS 1
S00_AXI.CONFIG.NUM_WRITE_THREADS 1
S00_AXI.CONFIG.DATA_WIDTH 32
S00_AXI.CONFIG.DATAWIDTH 32
S00_AXI.CONFIG.MAX_BURST_LENGTH 4
S00_AXI.CONFIG.FREQ_HZ 100000000
S00_AXI.CONFIG.HAS_PROT 1
S00_AXI.CONFIG.HAS_CACHE 1
S00_AXI.CONFIG.HAS_QOS 1
S00_AXI.CONFIG.HAS_REGION 0
S00_AXI.CONFIG.HAS_WSTRB 1
S00_AXI.CONFIG.HAS_BRESP 1
S00_AXI.CONFIG.HAS_RRESP 1
S00_AXI.CONFIG.PHASE 0.0
S00_AXI.CONFIG.CLK_DOMAIN /clk_wiz_0_clk_out1
S00_AXI.CONFIG.INSERT_VIP 0
S01_AXI.CONFIG.ID_WIDTH 0
S01_AXI.CONFIG.READ_WRITE_MODE READ_ONLY
S01_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
S01_AXI.CONFIG.HAS_BURST 1
S01_AXI.CONFIG.HAS_LOCK 0
S01_AXI.CONFIG.ADDR_WIDTH 36
S01_AXI.CONFIG.PROTOCOL AXI4
S01_AXI.CONFIG.AWUSER_WIDTH 0
S01_AXI.CONFIG.ARUSER_WIDTH 0
S01_AXI.CONFIG.WUSER_WIDTH 0
S01_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
S01_AXI.CONFIG.RUSER_WIDTH 0
S01_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
S01_AXI.CONFIG.BUSER_WIDTH 0
S01_AXI.CONFIG.DATA_WIDTH 32
S01_AXI.CONFIG.DATAWIDTH 32
S01_AXI.CONFIG.NUM_READ_OUTSTANDING 8
S01_AXI.CONFIG.NUM_READ_THREADS 1
S01_AXI.CONFIG.MAX_BURST_LENGTH 8
S01_AXI.CONFIG.HAS_WSTRB 0
S01_AXI.CONFIG.HAS_BRESP 0
S01_AXI.CONFIG.FREQ_HZ 100000000
S01_AXI.CONFIG.HAS_PROT 1
S01_AXI.CONFIG.HAS_CACHE 1
S01_AXI.CONFIG.HAS_QOS 1
S01_AXI.CONFIG.HAS_REGION 0
S01_AXI.CONFIG.HAS_RRESP 1
S01_AXI.CONFIG.NUM_WRITE_OUTSTANDING 2
S01_AXI.CONFIG.PHASE 0.0
S01_AXI.CONFIG.CLK_DOMAIN /clk_wiz_0_clk_out1
S01_AXI.CONFIG.NUM_WRITE_THREADS 1
S01_AXI.CONFIG.INSERT_VIP 0
M00_AXI.CONFIG.FREQ_HZ 200000000
M00_AXI.CONFIG.DATA_WIDTH 64
M00_AXI.CONFIG.DATAWIDTH 64
M00_AXI.CONFIG.PROTOCOL AXI4
M00_AXI.CONFIG.ID_WIDTH 4
M00_AXI.CONFIG.ADDR_WIDTH 32
M00_AXI.CONFIG.AWUSER_WIDTH 0
M00_AXI.CONFIG.ARUSER_WIDTH 0
M00_AXI.CONFIG.WUSER_WIDTH 0
M00_AXI.CONFIG.RUSER_WIDTH 0
M00_AXI.CONFIG.BUSER_WIDTH 0
M00_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
M00_AXI.CONFIG.HAS_BURST 1
M00_AXI.CONFIG.HAS_LOCK 1
M00_AXI.CONFIG.HAS_PROT 1
M00_AXI.CONFIG.HAS_CACHE 1
M00_AXI.CONFIG.HAS_QOS 1
M00_AXI.CONFIG.HAS_REGION 0
M00_AXI.CONFIG.HAS_WSTRB 1
M00_AXI.CONFIG.HAS_BRESP 1
M00_AXI.CONFIG.HAS_RRESP 1
M00_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
M00_AXI.CONFIG.NUM_READ_OUTSTANDING 8
M00_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
M00_AXI.CONFIG.MAX_BURST_LENGTH 256
M00_AXI.CONFIG.PHASE 0
M00_AXI.CONFIG.CLK_DOMAIN design_1_mig_7series_0_0_ui_clk
M00_AXI.CONFIG.NUM_READ_THREADS 1
M00_AXI.CONFIG.NUM_WRITE_THREADS 1
M00_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
M00_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
M00_AXI.CONFIG.INSERT_VIP 0
M00_AXI.IS_CASCADED 0
S00_AXI.IS_CASCADED 0
S01_AXI.IS_CASCADED 0
S00_AXI.NUM_SEG 1
S00_AXI.SEG000.BASE_ADDR 0x0000000100000000
S00_AXI.SEG000.SIZE 32
S00_AXI.SEG000.SUPPORTS_READ 1
S00_AXI.SEG000.SUPPORTS_WRITE 1
S00_AXI.SEG000.SECURE_READ 0
S00_AXI.SEG000.SECURE_WRITE 0
S00_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
S00_AXI.SEG000.PROTOCOL AXI4
S00_AXI.SEG000.DATA_WIDTH 64
S01_AXI.NUM_SEG 1
S01_AXI.SEG000.BASE_ADDR 0x0000000100000000
S01_AXI.SEG000.SIZE 32
S01_AXI.SEG000.SUPPORTS_READ 1
S01_AXI.SEG000.SUPPORTS_WRITE 1
S01_AXI.SEG000.SECURE_READ 0
S01_AXI.SEG000.SECURE_WRITE 0
S01_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
S01_AXI.SEG000.PROTOCOL AXI4
S01_AXI.SEG000.DATA_WIDTH 64
