{
  "design": {
    "design_info": {
      "boundary_crc": "0xFF1B8A62979B787B",
      "device": "xc7k325tffv676-1",
      "gen_directory": "../../../../mb_max.gen/sources_1/bd/design_1",
      "name": "design_1",
      "rev_ctrl_bd_flag": "RevCtrlBdOff",
      "synth_flow_mode": "Hierarchical",
      "tool_version": "2022.1",
      "validated": "true"
    },
    "design_tree": {
      "microblaze_0_axi_intc": "",
      "microblaze_0_xlconcat": "",
      "axi_uartlite_0": "",
      "axi_timer_0": "",
      "microblaze_0_axi_periph": {
        "xbar": "",
        "s00_couplers": {},
        "m00_couplers": {},
        "m01_couplers": {},
        "m02_couplers": {}
      },
      "mig_7series_0": "",
      "smartconnect_0": "",
      "clk_wiz_0": "",
      "mdm_1": "",
      "rst_mig_7series_0_100M_1": "",
      "microblaze_0": "",
      "microblaze_0_local_memory": {
        "dlmb_v10": "",
        "ilmb_v10": "",
        "dlmb_bram_if_cntlr": "",
        "ilmb_bram_if_cntlr": "",
        "lmb_bram": ""
      },
      "util_ds_buf_1": "",
      "util_ds_buf_2": ""
    },
    "interface_ports": {
      "SYS_CLK_0": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
        "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "200000000"
          }
        }
      },
      "uart_rtl_0": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:uart:1.0",
        "vlnv": "xilinx.com:interface:uart_rtl:1.0"
      },
      "DDR3_0": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0",
        "vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
        "parameters": {
          "AXI_ARBITRATION_SCHEME": {
            "value": "TDM",
            "value_src": "default"
          },
          "BURST_LENGTH": {
            "value": "8",
            "value_src": "default"
          },
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "CAS_LATENCY": {
            "value": "11",
            "value_src": "default"
          },
          "CAS_WRITE_LATENCY": {
            "value": "11",
            "value_src": "default"
          },
          "CS_ENABLED": {
            "value": "true",
            "value_src": "default"
          },
          "DATA_MASK_ENABLED": {
            "value": "true",
            "value_src": "default"
          },
          "DATA_WIDTH": {
            "value": "8",
            "value_src": "default"
          },
          "MEMORY_TYPE": {
            "value": "COMPONENTS",
            "value_src": "default"
          },
          "MEM_ADDR_MAP": {
            "value": "ROW_COLUMN_BANK",
            "value_src": "default"
          },
          "SLOT": {
            "value": "Single",
            "value_src": "default"
          },
          "TIMEPERIOD_PS": {
            "value": "1250",
            "value_src": "default"
          }
        }
      },
      "SYS_CLK_1": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
        "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "200000000"
          }
        }
      }
    },
    "ports": {
      "sys_rst_0": {
        "type": "rst",
        "direction": "I",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW",
            "value_src": "default"
          }
        }
      },
      "clk100M": {
        "type": "clk",
        "direction": "O",
        "parameters": {
          "CLK_DOMAIN": {
            "value": "/clk_wiz_0_clk_out1",
            "value_src": "ip_prop"
          },
          "FREQ_HZ": {
            "value": "100000000",
            "value_src": "ip_prop"
          },
          "FREQ_TOLERANCE_HZ": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "ip_prop"
          }
        }
      }
    },
    "components": {
      "microblaze_0_axi_intc": {
        "vlnv": "xilinx.com:ip:axi_intc:4.1",
        "xci_name": "design_1_microblaze_0_axi_intc_0",
        "xci_path": "ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xci",
        "inst_hier_path": "microblaze_0_axi_intc",
        "parameters": {
          "C_HAS_FAST": {
            "value": "1"
          }
        }
      },
      "microblaze_0_xlconcat": {
        "vlnv": "xilinx.com:ip:xlconcat:2.1",
        "xci_name": "design_1_microblaze_0_xlconcat_0",
        "xci_path": "ip/design_1_microblaze_0_xlconcat_0/design_1_microblaze_0_xlconcat_0.xci",
        "inst_hier_path": "microblaze_0_xlconcat"
      },
      "axi_uartlite_0": {
        "vlnv": "xilinx.com:ip:axi_uartlite:2.0",
        "xci_name": "design_1_axi_uartlite_0_0",
        "xci_path": "ip/design_1_axi_uartlite_0_0/design_1_axi_uartlite_0_0.xci",
        "inst_hier_path": "axi_uartlite_0",
        "parameters": {
          "C_BAUDRATE": {
            "value": "115200"
          }
        }
      },
      "axi_timer_0": {
        "vlnv": "xilinx.com:ip:axi_timer:2.0",
        "xci_name": "design_1_axi_timer_0_0",
        "xci_path": "ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xci",
        "inst_hier_path": "axi_timer_0"
      },
      "microblaze_0_axi_periph": {
        "vlnv": "xilinx.com:ip:axi_interconnect:2.1",
        "xci_path": "ip/design_1_microblaze_0_axi_periph_2/design_1_microblaze_0_axi_periph_2.xci",
        "inst_hier_path": "microblaze_0_axi_periph",
        "xci_name": "design_1_microblaze_0_axi_periph_2",
        "parameters": {
          "NUM_MI": {
            "value": "3"
          }
        },
        "interface_ports": {
          "S00_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M00_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M01_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M02_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          }
        },
        "ports": {
          "ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_RESET": {
                "value": "ARESETN"
              }
            }
          },
          "ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S00_ARESETN"
              }
            }
          },
          "S00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M00_ARESETN"
              }
            }
          },
          "M00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M01_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M01_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M01_ARESETN"
              }
            }
          },
          "M01_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M02_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M02_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M02_ARESETN"
              }
            }
          },
          "M02_ARESETN": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "xbar": {
            "vlnv": "xilinx.com:ip:axi_crossbar:2.1",
            "xci_name": "design_1_xbar_2",
            "xci_path": "ip/design_1_xbar_2/design_1_xbar_2.xci",
            "inst_hier_path": "microblaze_0_axi_periph/xbar",
            "parameters": {
              "NUM_MI": {
                "value": "3"
              },
              "NUM_SI": {
                "value": "1"
              },
              "STRATEGY": {
                "value": "0"
              }
            },
            "interface_ports": {
              "S00_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI",
                  "M01_AXI",
                  "M02_AXI"
                ]
              }
            }
          },
          "s00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "s00_couplers_to_s00_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m00_couplers_to_m00_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m01_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m01_couplers_to_m01_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m02_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m02_couplers_to_m02_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          }
        },
        "interface_nets": {
          "m00_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M00_AXI",
              "m00_couplers/M_AXI"
            ]
          },
          "m01_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M01_AXI",
              "m01_couplers/M_AXI"
            ]
          },
          "m02_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M02_AXI",
              "m02_couplers/M_AXI"
            ]
          },
          "microblaze_0_axi_periph_to_s00_couplers": {
            "interface_ports": [
              "S00_AXI",
              "s00_couplers/S_AXI"
            ]
          },
          "s00_couplers_to_xbar": {
            "interface_ports": [
              "s00_couplers/M_AXI",
              "xbar/S00_AXI"
            ]
          },
          "xbar_to_m00_couplers": {
            "interface_ports": [
              "xbar/M00_AXI",
              "m00_couplers/S_AXI"
            ]
          },
          "xbar_to_m01_couplers": {
            "interface_ports": [
              "xbar/M01_AXI",
              "m01_couplers/S_AXI"
            ]
          },
          "xbar_to_m02_couplers": {
            "interface_ports": [
              "xbar/M02_AXI",
              "m02_couplers/S_AXI"
            ]
          }
        },
        "nets": {
          "microblaze_0_axi_periph_ACLK_net": {
            "ports": [
              "ACLK",
              "xbar/aclk",
              "s00_couplers/S_ACLK",
              "s00_couplers/M_ACLK",
              "m00_couplers/M_ACLK",
              "m01_couplers/M_ACLK",
              "m02_couplers/M_ACLK",
              "m00_couplers/S_ACLK",
              "m01_couplers/S_ACLK",
              "m02_couplers/S_ACLK"
            ]
          },
          "microblaze_0_axi_periph_ARESETN_net": {
            "ports": [
              "ARESETN",
              "xbar/aresetn",
              "s00_couplers/S_ARESETN",
              "s00_couplers/M_ARESETN",
              "m00_couplers/M_ARESETN",
              "m01_couplers/M_ARESETN",
              "m02_couplers/M_ARESETN",
              "m00_couplers/S_ARESETN",
              "m01_couplers/S_ARESETN",
              "m02_couplers/S_ARESETN"
            ]
          }
        }
      },
      "mig_7series_0": {
        "vlnv": "xilinx.com:ip:mig_7series:4.2",
        "xci_name": "design_1_mig_7series_0_0",
        "xci_path": "ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci",
        "inst_hier_path": "mig_7series_0",
        "parameters": {
          "BOARD_MIG_PARAM": {
            "value": "Custom"
          },
          "MIG_DONT_TOUCH_PARAM": {
            "value": "Custom"
          },
          "RESET_BOARD_INTERFACE": {
            "value": "Custom"
          },
          "XML_INPUT_FILE": {
            "value": "mig_a.prj"
          }
        }
      },
      "smartconnect_0": {
        "vlnv": "xilinx.com:ip:smartconnect:1.0",
        "xci_name": "design_1_smartconnect_0_0",
        "xci_path": "ip/design_1_smartconnect_0_0/design_1_smartconnect_0_0.xci",
        "inst_hier_path": "smartconnect_0",
        "parameters": {
          "NUM_CLKS": {
            "value": "2"
          }
        },
        "interface_ports": {
          "S00_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "NUM_READ_OUTSTANDING": {
                "value": "2"
              },
              "NUM_WRITE_OUTSTANDING": {
                "value": "32"
              }
            },
            "bridges": [
              "M00_AXI"
            ]
          },
          "S01_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "NUM_READ_OUTSTANDING": {
                "value": "8"
              },
              "NUM_WRITE_OUTSTANDING": {
                "value": "2"
              }
            },
            "bridges": [
              "M00_AXI"
            ]
          },
          "M00_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "MAX_BURST_LENGTH": {
                "value": "4"
              },
              "NUM_READ_OUTSTANDING": {
                "value": "8"
              },
              "NUM_READ_THREADS": {
                "value": "1"
              },
              "NUM_WRITE_OUTSTANDING": {
                "value": "32"
              },
              "NUM_WRITE_THREADS": {
                "value": "1"
              },
              "RUSER_BITS_PER_BYTE": {
                "value": "0"
              },
              "SUPPORTS_NARROW_BURST": {
                "value": "0"
              },
              "WUSER_BITS_PER_BYTE": {
                "value": "0"
              }
            }
          }
        }
      },
      "clk_wiz_0": {
        "vlnv": "xilinx.com:ip:clk_wiz:6.0",
        "xci_name": "design_1_clk_wiz_0_0",
        "xci_path": "ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci",
        "inst_hier_path": "clk_wiz_0",
        "parameters": {
          "CLKIN1_JITTER_PS": {
            "value": "50.0"
          },
          "CLKOUT1_JITTER": {
            "value": "112.316"
          },
          "CLKOUT1_PHASE_ERROR": {
            "value": "89.971"
          },
          "CLKOUT2_JITTER": {
            "value": "98.146"
          },
          "CLKOUT2_PHASE_ERROR": {
            "value": "89.971"
          },
          "CLKOUT2_REQUESTED_OUT_FREQ": {
            "value": "200.000"
          },
          "CLKOUT2_USED": {
            "value": "true"
          },
          "MMCM_CLKFBOUT_MULT_F": {
            "value": "5.000"
          },
          "MMCM_CLKIN1_PERIOD": {
            "value": "5.000"
          },
          "MMCM_CLKIN2_PERIOD": {
            "value": "10.0"
          },
          "MMCM_CLKOUT1_DIVIDE": {
            "value": "5"
          },
          "NUM_OUT_CLKS": {
            "value": "2"
          },
          "PRIM_IN_FREQ": {
            "value": "200.000"
          },
          "PRIM_SOURCE": {
            "value": "Single_ended_clock_capable_pin"
          },
          "USE_RESET": {
            "value": "false"
          }
        }
      },
      "mdm_1": {
        "vlnv": "xilinx.com:ip:mdm:3.2",
        "xci_name": "design_1_mdm_1_1",
        "xci_path": "ip/design_1_mdm_1_1/design_1_mdm_1_1.xci",
        "inst_hier_path": "mdm_1"
      },
      "rst_mig_7series_0_100M_1": {
        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
        "xci_name": "design_1_rst_mig_7series_0_100M_1_0",
        "xci_path": "ip/design_1_rst_mig_7series_0_100M_1_0/design_1_rst_mig_7series_0_100M_1_0.xci",
        "inst_hier_path": "rst_mig_7series_0_100M_1"
      },
      "microblaze_0": {
        "vlnv": "xilinx.com:ip:microblaze:11.0",
        "xci_name": "design_1_microblaze_0_3",
        "xci_path": "ip/design_1_microblaze_0_3/design_1_microblaze_0_3.xci",
        "inst_hier_path": "microblaze_0",
        "parameters": {
          "C_ADDR_SIZE": {
            "value": "36"
          },
          "C_ADDR_TAG_BITS": {
            "value": "17"
          },
          "C_DCACHE_ADDR_TAG": {
            "value": "17"
          },
          "C_DEBUG_ENABLED": {
            "value": "1"
          },
          "C_D_AXI": {
            "value": "1"
          },
          "C_D_LMB": {
            "value": "1"
          },
          "C_I_LMB": {
            "value": "1"
          },
          "C_M_AXI_DC_ADDR_WIDTH": {
            "value": "36"
          },
          "C_M_AXI_DP_ADDR_WIDTH": {
            "value": "36"
          },
          "C_M_AXI_IC_ADDR_WIDTH": {
            "value": "36"
          },
          "C_M_AXI_IP_ADDR_WIDTH": {
            "value": "36"
          },
          "C_USE_DCACHE": {
            "value": "1"
          },
          "C_USE_ICACHE": {
            "value": "1"
          },
          "G_TEMPLATE_LIST": {
            "value": "10"
          }
        },
        "interface_ports": {
          "DLMB": {
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0x000FFFFFFFFF",
              "width": "36"
            }
          },
          "ILMB": {
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Instruction",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0x000FFFFFFFFF",
              "width": "36"
            }
          },
          "M_AXI_DP": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0x000FFFFFFFFF",
              "width": "36"
            }
          },
          "M_AXI_DC": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0x000FFFFFFFFF",
              "width": "36"
            },
            "parameters": {
              "master_id": {
                "value": "1"
              }
            }
          },
          "M_AXI_IC": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Instruction",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0x000FFFFFFFFF",
              "width": "36"
            },
            "parameters": {
              "master_id": {
                "value": "2"
              }
            }
          }
        },
        "addressing": {
          "address_spaces": {
            "Data": {
              "range": "64G",
              "width": "36"
            },
            "Instruction": {
              "range": "64G",
              "width": "36"
            }
          }
        },
        "hdl_attributes": {
          "BMM_INFO_PROCESSOR": {
            "value": "microblaze-le > design_1 microblaze_0_local_memory/dlmb_bram_if_cntlr",
            "value_src": "default"
          },
          "KEEP_HIERARCHY": {
            "value": "yes",
            "value_src": "default"
          }
        }
      },
      "microblaze_0_local_memory": {
        "interface_ports": {
          "DLMB": {
            "mode": "MirroredMaster",
            "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0",
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0"
          },
          "ILMB": {
            "mode": "MirroredMaster",
            "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0",
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0"
          }
        },
        "ports": {
          "LMB_Clk": {
            "type": "clk",
            "direction": "I"
          },
          "SYS_Rst": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "dlmb_v10": {
            "vlnv": "xilinx.com:ip:lmb_v10:3.0",
            "xci_name": "design_1_dlmb_v10_2",
            "xci_path": "ip/design_1_dlmb_v10_2/design_1_dlmb_v10_2.xci",
            "inst_hier_path": "microblaze_0_local_memory/dlmb_v10",
            "interface_ports": {
              "LMB_M": {
                "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
                "mode": "MirroredMaster",
                "bridges": [
                  "LMB_Sl_0"
                ]
              }
            }
          },
          "ilmb_v10": {
            "vlnv": "xilinx.com:ip:lmb_v10:3.0",
            "xci_name": "design_1_ilmb_v10_2",
            "xci_path": "ip/design_1_ilmb_v10_2/design_1_ilmb_v10_2.xci",
            "inst_hier_path": "microblaze_0_local_memory/ilmb_v10",
            "interface_ports": {
              "LMB_M": {
                "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
                "mode": "MirroredMaster",
                "bridges": [
                  "LMB_Sl_0"
                ]
              }
            }
          },
          "dlmb_bram_if_cntlr": {
            "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
            "xci_name": "design_1_dlmb_bram_if_cntlr_2",
            "xci_path": "ip/design_1_dlmb_bram_if_cntlr_2/design_1_dlmb_bram_if_cntlr_2.xci",
            "inst_hier_path": "microblaze_0_local_memory/dlmb_bram_if_cntlr",
            "parameters": {
              "C_ECC": {
                "value": "0"
              }
            },
            "hdl_attributes": {
              "BMM_INFO_ADDRESS_SPACE": {
                "value": "byte  0x00000000 32 > design_1 microblaze_0_local_memory/lmb_bram",
                "value_src": "default"
              },
              "KEEP_HIERARCHY": {
                "value": "yes",
                "value_src": "default"
              }
            }
          },
          "ilmb_bram_if_cntlr": {
            "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
            "xci_name": "design_1_ilmb_bram_if_cntlr_2",
            "xci_path": "ip/design_1_ilmb_bram_if_cntlr_2/design_1_ilmb_bram_if_cntlr_2.xci",
            "inst_hier_path": "microblaze_0_local_memory/ilmb_bram_if_cntlr",
            "parameters": {
              "C_ECC": {
                "value": "0"
              }
            }
          },
          "lmb_bram": {
            "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
            "xci_name": "design_1_lmb_bram_2",
            "xci_path": "ip/design_1_lmb_bram_2/design_1_lmb_bram_2.xci",
            "inst_hier_path": "microblaze_0_local_memory/lmb_bram",
            "parameters": {
              "Memory_Type": {
                "value": "True_Dual_Port_RAM"
              },
              "use_bram_block": {
                "value": "BRAM_Controller"
              }
            }
          }
        },
        "interface_nets": {
          "microblaze_0_dlmb": {
            "interface_ports": [
              "DLMB",
              "dlmb_v10/LMB_M"
            ]
          },
          "microblaze_0_dlmb_bus": {
            "interface_ports": [
              "dlmb_v10/LMB_Sl_0",
              "dlmb_bram_if_cntlr/SLMB"
            ]
          },
          "microblaze_0_dlmb_cntlr": {
            "interface_ports": [
              "dlmb_bram_if_cntlr/BRAM_PORT",
              "lmb_bram/BRAM_PORTA"
            ]
          },
          "microblaze_0_ilmb": {
            "interface_ports": [
              "ILMB",
              "ilmb_v10/LMB_M"
            ]
          },
          "microblaze_0_ilmb_bus": {
            "interface_ports": [
              "ilmb_v10/LMB_Sl_0",
              "ilmb_bram_if_cntlr/SLMB"
            ]
          },
          "microblaze_0_ilmb_cntlr": {
            "interface_ports": [
              "ilmb_bram_if_cntlr/BRAM_PORT",
              "lmb_bram/BRAM_PORTB"
            ]
          }
        },
        "nets": {
          "SYS_Rst_1": {
            "ports": [
              "SYS_Rst",
              "dlmb_v10/SYS_Rst",
              "dlmb_bram_if_cntlr/LMB_Rst",
              "ilmb_v10/SYS_Rst",
              "ilmb_bram_if_cntlr/LMB_Rst"
            ]
          },
          "microblaze_0_Clk": {
            "ports": [
              "LMB_Clk",
              "dlmb_v10/LMB_Clk",
              "dlmb_bram_if_cntlr/LMB_Clk",
              "ilmb_v10/LMB_Clk",
              "ilmb_bram_if_cntlr/LMB_Clk"
            ]
          }
        }
      },
      "util_ds_buf_1": {
        "vlnv": "xilinx.com:ip:util_ds_buf:2.2",
        "xci_name": "design_1_util_ds_buf_1_0",
        "xci_path": "ip/design_1_util_ds_buf_1_0/design_1_util_ds_buf_1_0.xci",
        "inst_hier_path": "util_ds_buf_1"
      },
      "util_ds_buf_2": {
        "vlnv": "xilinx.com:ip:util_ds_buf:2.2",
        "xci_name": "design_1_util_ds_buf_1_1",
        "xci_path": "ip/design_1_util_ds_buf_1_1/design_1_util_ds_buf_1_1.xci",
        "inst_hier_path": "util_ds_buf_2"
      }
    },
    "interface_nets": {
      "SYS_CLK_0_1": {
        "interface_ports": [
          "SYS_CLK_0",
          "util_ds_buf_2/CLK_IN_D"
        ]
      },
      "SYS_CLK_1_1": {
        "interface_ports": [
          "SYS_CLK_1",
          "util_ds_buf_1/CLK_IN_D"
        ]
      },
      "axi_uartlite_0_UART": {
        "interface_ports": [
          "uart_rtl_0",
          "axi_uartlite_0/UART"
        ]
      },
      "microblaze_0_M_AXI_DC": {
        "interface_ports": [
          "microblaze_0/M_AXI_DC",
          "smartconnect_0/S00_AXI"
        ]
      },
      "microblaze_0_M_AXI_IC": {
        "interface_ports": [
          "microblaze_0/M_AXI_IC",
          "smartconnect_0/S01_AXI"
        ]
      },
      "microblaze_0_axi_dp": {
        "interface_ports": [
          "microblaze_0_axi_periph/S00_AXI",
          "microblaze_0/M_AXI_DP"
        ]
      },
      "microblaze_0_axi_periph_M00_AXI": {
        "interface_ports": [
          "microblaze_0_axi_periph/M00_AXI",
          "axi_timer_0/S_AXI"
        ]
      },
      "microblaze_0_axi_periph_M01_AXI": {
        "interface_ports": [
          "microblaze_0_axi_periph/M01_AXI",
          "axi_uartlite_0/S_AXI"
        ]
      },
      "microblaze_0_axi_periph_M02_AXI": {
        "interface_ports": [
          "microblaze_0_axi_periph/M02_AXI",
          "microblaze_0_axi_intc/s_axi"
        ]
      },
      "microblaze_0_debug": {
        "interface_ports": [
          "mdm_1/MBDEBUG_0",
          "microblaze_0/DEBUG"
        ]
      },
      "microblaze_0_dlmb_1": {
        "interface_ports": [
          "microblaze_0/DLMB",
          "microblaze_0_local_memory/DLMB"
        ]
      },
      "microblaze_0_ilmb_1": {
        "interface_ports": [
          "microblaze_0/ILMB",
          "microblaze_0_local_memory/ILMB"
        ]
      },
      "microblaze_0_interrupt": {
        "interface_ports": [
          "microblaze_0_axi_intc/interrupt",
          "microblaze_0/INTERRUPT"
        ]
      },
      "mig_7series_0_DDR3": {
        "interface_ports": [
          "DDR3_0",
          "mig_7series_0/DDR3"
        ]
      },
      "smartconnect_0_M00_AXI": {
        "interface_ports": [
          "smartconnect_0/M00_AXI",
          "mig_7series_0/S_AXI"
        ]
      }
    },
    "nets": {
      "axi_timer_0_interrupt": {
        "ports": [
          "axi_timer_0/interrupt",
          "microblaze_0_xlconcat/In0"
        ]
      },
      "axi_uartlite_0_interrupt": {
        "ports": [
          "axi_uartlite_0/interrupt",
          "microblaze_0_xlconcat/In1"
        ]
      },
      "clk_wiz_0_locked": {
        "ports": [
          "clk_wiz_0/locked",
          "rst_mig_7series_0_100M_1/dcm_locked"
        ]
      },
      "mdm_1_debug_sys_rst": {
        "ports": [
          "mdm_1/Debug_SYS_Rst",
          "rst_mig_7series_0_100M_1/mb_debug_sys_rst"
        ]
      },
      "microblaze_0_Clk": {
        "ports": [
          "clk_wiz_0/clk_out1",
          "rst_mig_7series_0_100M_1/slowest_sync_clk",
          "clk100M",
          "axi_timer_0/s_axi_aclk",
          "axi_uartlite_0/s_axi_aclk",
          "smartconnect_0/aclk1",
          "microblaze_0/Clk",
          "microblaze_0_axi_periph/ACLK",
          "microblaze_0_axi_periph/S00_ACLK",
          "microblaze_0_axi_periph/M00_ACLK",
          "microblaze_0_axi_periph/M01_ACLK",
          "microblaze_0_axi_periph/M02_ACLK",
          "microblaze_0_axi_intc/s_axi_aclk",
          "microblaze_0_axi_intc/processor_clk",
          "microblaze_0_local_memory/LMB_Clk"
        ]
      },
      "microblaze_0_intr": {
        "ports": [
          "microblaze_0_xlconcat/dout",
          "microblaze_0_axi_intc/intr"
        ]
      },
      "mig_7series_0_ui_clk": {
        "ports": [
          "mig_7series_0/ui_clk",
          "smartconnect_0/aclk",
          "mig_7series_0/clk_ref_i"
        ]
      },
      "rst_mig_7series_0_100M_1_bus_struct_reset": {
        "ports": [
          "rst_mig_7series_0_100M_1/bus_struct_reset",
          "microblaze_0_local_memory/SYS_Rst"
        ]
      },
      "rst_mig_7series_0_100M_1_interconnect_aresetn": {
        "ports": [
          "rst_mig_7series_0_100M_1/interconnect_aresetn",
          "smartconnect_0/aresetn",
          "microblaze_0_axi_periph/M02_ARESETN",
          "microblaze_0_axi_periph/S00_ARESETN",
          "microblaze_0_axi_periph/M01_ARESETN",
          "microblaze_0_axi_periph/M00_ARESETN",
          "microblaze_0_axi_periph/ARESETN"
        ]
      },
      "rst_mig_7series_0_100M_1_mb_reset": {
        "ports": [
          "rst_mig_7series_0_100M_1/mb_reset",
          "microblaze_0/Reset",
          "microblaze_0_axi_intc/processor_rst"
        ]
      },
      "rst_mig_7series_0_100M_peripheral_aresetn": {
        "ports": [
          "rst_mig_7series_0_100M_1/peripheral_aresetn",
          "axi_timer_0/s_axi_aresetn",
          "axi_uartlite_0/s_axi_aresetn",
          "microblaze_0_axi_intc/s_axi_aresetn",
          "mig_7series_0/aresetn"
        ]
      },
      "sys_rst_0_1": {
        "ports": [
          "sys_rst_0",
          "rst_mig_7series_0_100M_1/ext_reset_in",
          "mig_7series_0/sys_rst"
        ]
      },
      "util_ds_buf_1_IBUF_OUT": {
        "ports": [
          "util_ds_buf_2/IBUF_OUT",
          "clk_wiz_0/clk_in1",
          "mig_7series_0/sys_clk_i"
        ]
      }
    },
    "addressing": {
      "/microblaze_0": {
        "address_spaces": {
          "Data": {
            "segments": {
              "SEG_axi_timer_0_Reg": {
                "address_block": "/axi_timer_0/S_AXI/Reg",
                "offset": "0x041C00000",
                "range": "64K"
              },
              "SEG_axi_uartlite_0_Reg": {
                "address_block": "/axi_uartlite_0/S_AXI/Reg",
                "offset": "0x040600000",
                "range": "64K"
              },
              "SEG_dlmb_bram_if_cntlr_Mem": {
                "address_block": "/microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem",
                "offset": "0x000000000",
                "range": "128K",
                "offset_high_param": "C_HIGHADDR"
              },
              "SEG_microblaze_0_axi_intc_Reg": {
                "address_block": "/microblaze_0_axi_intc/S_AXI/Reg",
                "offset": "0x041200000",
                "range": "64K"
              },
              "SEG_mig_7series_0_memaddr": {
                "address_block": "/mig_7series_0/memmap/memaddr",
                "offset": "0x100000000",
                "range": "4G"
              }
            }
          },
          "Instruction": {
            "segments": {
              "SEG_ilmb_bram_if_cntlr_Mem": {
                "address_block": "/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem",
                "offset": "0x000000000",
                "range": "128K",
                "offset_high_param": "C_HIGHADDR"
              },
              "SEG_mig_7series_0_memaddr": {
                "address_block": "/mig_7series_0/memmap/memaddr",
                "offset": "0x100000000",
                "range": "4G"
              }
            }
          }
        }
      }
    }
  }
}