
##set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_2/U0/IBUF_OUT[0]]


#	design_1_i/util_ds_buf_1/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I (IBUFDS.O) is locked to IOB_X0Y26
#	 design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKIN1) is locked to PLLE2_ADV_X1Y1

set_property IOSTANDARD LVCMOS12 [get_ports sys_rst_0]
set_property PACKAGE_PIN V21 [get_ports sys_rst_0]
set_property IOSTANDARD LVCMOS25 [get_ports uart_rtl_0_rxd]
set_property IOSTANDARD LVCMOS25 [get_ports uart_rtl_0_txd]
set_property PACKAGE_PIN A15 [get_ports uart_rtl_0_txd]
set_property PACKAGE_PIN A13 [get_ports uart_rtl_0_rxd]

set_property IOSTANDARD LVCMOS12 [get_ports led1]
set_property PACKAGE_PIN AA25 [get_ports led1]
set_property IOSTANDARD LVCMOS12 [get_ports led2]
set_property PACKAGE_PIN W24 [get_ports led2]

##set_property PACKAGE_PIN Y23 [get_ports SYS_CLK_0_clk_p]
##set_property PACKAGE_PIN AA24 [get_ports SYS_CLK_0_clk_n]
##set_property IOSTANDARD DIFF_HSUL_12 [get_ports SYS_CLK_0_clk_p]
##set_property IOSTANDARD DIFF_HSUL_12 [get_ports SYS_CLK_0_clk_n]

set_property PACKAGE_PIN AB11 [get_ports SYS_CLK_0_clk_p]
set_property PACKAGE_PIN AC11 [get_ports SYS_CLK_0_clk_n]
set_property IOSTANDARD DIFF_SSTL15 [get_ports SYS_CLK_0_clk_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports SYS_CLK_0_clk_n]

set_property IOSTANDARD DIFF_HSUL_12 [get_ports SYS_CLK_1_clk_p]
set_property PACKAGE_PIN Y23 [get_ports SYS_CLK_1_clk_p]


set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk100M]
